ارائه یک توسعه شی گرا برای ‏‎vhdl‎‏ و ترجمه آن به ‏‎vhdl‎‏ استاندارد

RTL VHDL Behavioral VHDL Test Generator Behavioral VHDL Simulator VHDL Simulator Switch Level

ovhdl :یک پیشنهاد برای توسعه vhdl به سمت شیءگرایی

در طراحی سیستمهای بزرگ و پیچیده روش تجزیه و تحلیل داده گرا یا شیءگرا در مقابل روش تجزیه و تحلیل الگوریتمی، نمایی ساختیافته تر و قابل کنترل بیشتر در اختیار طراح می گذارد. این مهم با تحقق مفاهیمی همچون تجرید ، مخفی سازی اطلاعات ، رعغایت ساختار سلسله مراتبی ، ماژولار و پارامتریزه بودن طرح قابل دسترسی است . vhdl به عنوان یک زبان شناخته شده توصیف سخت افزار برای تجزیه و تحلیل الگوریتمی مناسب است ، ول...

VHDL Concepts

This paper presents a formal model of several fundamental concepts in VHDL including the semantics of individual concurrent statements, and groups of those statements, resolution functions, delta delays, and hierarchical component structuring. Based on this model, several extensions to VHDL are proposed, including nondeterministic assignments and unbounded asynchrony. Nondeterminism allows the ...

Formal verification of VHDL using VHDL-like ACL2 models

When a design reaches the register transfer level, essential architectural decisions have been taken; their validation required extensive simulation of the abstract behavioral specifications. The recognized need for formal verification cannot be met by current automatic equivalence and model checking tools, which mainly apply to logic synthesis inputs and outputs, or require manual abstraction....

Standard Verilog-VHDL Interoperability

During the last few years HDLs have become the driver behind the move to top down design in the electronic design industry. Two HDLs, VHDL and Verilog HDL have become the dominant de facto industry standard HDLs. Since the industry has made a hugh investment in both HDLs and there is every indication that each will retain significant market share for the foreseeable future, it is critical that ...

Sli ing for VHDL ?