During the past few years, a lot of work has been done on behavioral models and simulation tools. But a need for modeling strategy still remains. The VHDL-AMS language supports the description of analog electronic circuits using Ordinary Differential Algebraic Equations (ODAEs), in addition to its support for describing discrete-event systems. For VHDL-AMS to be useful to the analog design ...

System design is typically done in VHDL to facilitate top-down design and to enable the mapping of a design to many implementations. Reusabil-ity of subsystems to date has largely been performed with libraries of synthesizable VHDL subsystems. This paper presents recommended extensions to VHDL to allow the VHDL designer to interact with nonsynthesizable subsystems while still designing in VHDL....

Designers face the challenge of specifying and implementing complicated mixed-technology systems. In order to better address mixed-signal designs, the VHDL-AMS and Verilog-AMS languages have been developed. These languages provide powerful capabilities to model and simulate behaviors in both the continuous and discrete time domains. Contemporaneously, the control systems community developed the...

One of the major problems within the VHDL based behavioral synthesis is to start the design on higher abstraction level than the register transfer level (RTL). VHDL semantics was designed strictly for simulation, therefore it was not considered as high-level synthesis language. A novel synthesis procedure was developed, which uses the methodology of high level synthesis. It starts from an abstr...

Goossens defined a structural operational semantics for a subset of VHDL-87 and proved that the parallelism present in VHDL is benign. We extend this work to include VHDL-93 features such as shared variables and postponed processes that change the underlying semantic model. In the presence of shared variables, non-deterministic execution of VHDL-93 processes destroys the unique meaning property...

The VHDL language is considered to be an important standard among the hardware description tools. Most of the existing loop optimization techniques that consider the parallelism inherent to multi-dimensional problems depend on loop transformations not available in the current VHDL Synthesis products. This study presents a coding technique on modeling multi-dimensional (nested) loops on VHDL, wh...