This paper presents the VHDL implementation of fault tolerant cellular genetic algorithm. The goal of paper is to harden the hardware implementation of the cGA against single error upset (SEU), when affecting the fitness registers in the target hardware. The proposed approach, consists of two phases; Error monitoring and error recovery. Using innovative connectivity between processing elements ...

Memory Errors Detection and Correction aim to secure the transaction of data between the central processing unit of a satellite onboard computer and its local memory. In this paper, the application of a double-bit error detection and correction method is described and implemented in Field Programmable Gate Array (FPGA) technology. The performance of the proposed EDAC method is measured and comp...

During FPGA configuration, the error detection CRC feature detects configuration bitstream corruption when the bitstream is transferred from an external device into the FPGA. In user mode, the error detection CRC feature detects a single event upset (SEU) and determines the error type and location. In addition, Arria V, Cyclone V, and Stratix V devices support internal scrubbing, an ability to ...

Radiation in space is potentially hazardous to microelectronic circuits and systems such as spacecraft electronics. Transient effects on circuits and systems from high energetic particles can interrupt electronics operation or crash the systems. This phenomenon is particularly serious in complementary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) since most of modern ICs are implem...

In this paper, we present a new technique to improve the reliability of SRAMs used in space radiation environments. This technique deals with the SRAM power-bus monitoring by using Built-In Current Sensor (BICS) circuits that detect abnormal current dissipation in the memory power-bus. This abnormal current is the result of a single-event upset (SEU) in the memory and it is generated during the...

With device size shrinking and fast rising frequency ranges, effect of cosmic radiations and alpha particles known as Single-Event-Upset (SEU), Single-Eventtransients (SET), is a growing concern in logic circuits. Accurate understanding and estimation of Single-EventUpset sensitivities of individual nodes is necessary to achieve better soft error hardening techniques at logic level design abstr...

We measure distributions of heavy-ioninduced Single Event Transient (SET) pulse widths from the 4 kinds of inverter chains to measure their characteristics and estimate SET-induced soft error rates on a Flip-Flop (FF) and a delayed TMR FF. Test chip was fabricated in 65-nm bulk CMOS process and measurement results show that maximum SETinduced soft error rate on a FF is equivalent to 20% of Sing...

The application of Static Random-Access Memory (SRAM), becomes more and more widely in aviation. However, the large amount of SRAM cells is very vulnerable to radiation included single-event upset (SEU). Based on the detection requirement of SRAM’s SEU, the detected circuit of the SEU on SRAM is designed. Then the method of redundancy check is used in the reinforcement of the SEU. The test resu...

This paper addresses the issue of Single-Event Upset (SEU) in quasi delay-insensitive (QDI) asynchronous circuits. We show that an SEU can cause abnormal computations in QDI circuits beside deadlock, and we propose a general method to make QDI circuits SEU-tolerant. We present a simplified SEUtolerant buffer implementations for CMOS technology. Finally, we present a case study of a one-bit comp...

Total ionizing dose (TID) effects and single event effects (SEE) in antifuse-, Flash-, and SRAM-based field programmable gate arrays (FPGAs) are reviewed. There is a brief discussion of the programmable element impact on the FPGA architecture. In the following sections, most radiation data are from antifuse-based FPGAs. The basic TID mechanisms are introduced and used to explain the anomalies i...