Hetero-structure tunnel junctions in non-planar gate-all-around nanowire (GAA NW) tunnel FETs (TFETs) have shown significant enhancement in 'ON' state tunnel current over their all-silicon counterpart. Here we show the unique concept of nanotube TFET in a hetero-structure configuration that is capable of much higher drive current as opposed to that of GAA NW TFETs.Through the use of inner/outer...

In this paper, we have presented a heterojunction gate all around nanowiretunneling field effect transistor (GAA NW TFET) and have explained its characteristicsin details. The proposed device has been structured using Germanium for source regionand Silicon for channel and drain regions. Kane's band-to-band tunneling model hasbeen used to account for the amount of band-to...

This research paper explains the effect of dimensions Gate-all-around Si nanowire tunneling field transistor (GAA Si-NW TFET) on ON/OFF current ratio, drain induces barrier lowering (DIBL), sub-threshold swing (SS), and threshold voltage (VT). These parameters are critical factors characteristics tunnel transistors. The Silvaco TCAD has been used to study electrical TFET. Output (gate voltage-d...

In this paper, we propose and validate a Heterogate DielectricDual Material Gate-Gate All Around, Tunnel Field Effect Transistor (HD-DMG-GAA-TFET). A comparative study for different values of high-k has been done, and it has been clearly shown that the problem of lower ION (which hinders the circuit performance of TFET) can be overcome by using the dielectric engineered hetero-gate architecture...

Tunneling field-effect transistors (TFETs) are very applicable to low standby-power application by their virtues of low off-current (Ioff) and small subthreshold swing (S). However, low on-current (Ion) of silicon-based TFETs has been pointed out as a drawback. To improve Ion of TFET, a gate-all-around (GAA) TFET based on III-V compound semiconductor with InAs/InGaAs/InP multiple-heterojunction...

This paper explains the performance analysis of Gate-AllAround silicon nanowire with 80nm diameter field effect transistor based CMOS based device utilizing the 45-nm technology. Simulation and analysis of nanowire (NW) CMOS inverter show that there is the reduction of 70% in leakage power and delay minimization of 25% as compared with 180 nm channel length.Gate-All-Aorund (GAA) configuration p...

The tunnel field-effect transistor (TFET) is considered a promising next-generation due to its potentially limit-breaking low subthreshold swing and better immunity against short-channel effects. However, the ON-state current (ION) of TFETs has been critical problem. In this work, we investigated effects source doping concentration gradient (SDG) on ION n-type Si gate-all-around (GAA) nanowire ...

In this thesis innovative tunnel devices based on new architectures, new fabrication approaches and novel material combinations are fabricated and investigated in detail. In particular, nanowire homoand heterojunction tunnel diodes based on Si and InAs-Si have been demonstrated for the rst time. The gained knowledge and understanding of tunnel diodes is applied to design and fabricate InAs-Si h...

In the proposed work an analytical model of a p-channel dual material gate all around tunnel FET (DMGAA-TFET) is presented and its performance is compared with the conventional GAA-TFET. The electrostatic potential profile of the model is obtained using 2-D Laplace’s solution in the cylindrical coordinate system. A quantitative study of the drain current has been carried out using electric fiel...

In this paper, for the first time, the square-shaped extended source tunneling field-effect transistor (SES TFET) by means of the silicon carbide polytype (3C-SiC) and dopant pocket layer has been presented. By inserting the silicon carbide polytype as substrate and n-type pocket in the channel at the source edge, on-current is increased by about 10 times compared with the conventional SES TFET...