Routing tools consume a signiicant portion of the total design time. Considering routability at earlier steps of the CAD ow would both yield better quality and faster design process. In this paper we are presenting a routability-driven clustering method for cluster-based FPGAs. Our method packs LUTs into logic clusters while incorporating routability metrics into a cost function. The objective ...

Most of an FPGA s area and delay are due to routing Considering routability at earlier steps of the CAD ow would both yield better quality and faster design process In this paper we discuss the metrics that a ect routability in packing logic into clusters We are presenting a routability driven clustering method for cluster based FPGAs Our method packs LUTs into logic clusters while incorporatin...

In this paper we study the correlation between wirelength and routability for standard-cell placement problem, under the fixed-die place-androute environment. We present a placement tool with better routability for designs with high row utilization. Compared to a well-known industrial placement tool, our placer produces placements with equal or better routability, 13.2% better half-perimeter wi...

The prevalence of net list synthesis took raises great concern on routability of cell placement created with state-of-the-art placement techniques. In this paper, an accurate and efiienr placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach. This accurate and eficient modeling is based on the supply versus demand analysis of routi...

In this paper we study the correlation between wirelength and routability for standard-cell placement problem, under the modern place-androute environment. We present a placement tool named Dragon (version 2.1), and show its ability to produce good quality placement for designs with high row utilization. Compared to an industrial placer and an academic state-of-the-art placer, Dragon can produc...

abstract Many performance-driven routing algorithms do not consider routability. Routing trees are built assuming that there are no other wires. The main reason for this is that it is NP-hard to guarantee routability. Even checking for routabil-ity is a time-consuming process. This limits the usefulness of many performance-driven routing algorithms because unroutable designs are useless. Previo...

| In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial ow graph, for the e cient routability checking.

We address the problem of checking the routability of segmented channels using satisfiability. The segmented channel routing problem arises in the context of row-based field programmable gate array (FPGAs). Our approach transforms the routing task into a single large Boolean equation such that any assignment of input variables that satisfies the equation specifies a valid routing. It considers ...