نتایج جستجو برای: retention leakage noise low
تعداد نتایج: 1442580 فیلتر نتایج به سال:
Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in a...
Speed, power consumption and area, are some of the most important factors of concern in modern day memory design. As we move towards Deep Sub-Micron Technologies, the problems of leakage current, noise and cell stability due to physical parameter variation becomes more pronounced. In this paper we have designed an 8T Read Decoupled Dual Port SRAM Cell with Dual Threshold Voltage and characteriz...
A new Row-by-Row Dynamic Source-line Voltage control (RRDSV) scheme is proposed to reduce the active leakage as well as the stand-by leakage in SRAM. By dynamically controlling the source-line voltage of cells row by row, the cell leakage through inactive cells can be reduced by two orders of magnitude. Moreover, the bit-line leakage through pass transistors can be completely cut off. This leak...
.............................................................................................................................. viii Table of
growing demands and requires of high data rate systems cause significant increase of high frequency systems for wideband communication applications. as mixers are one of the main blocks of each receivers and its performance has great impact on receiver’s performance; in this thesis, a new solution for ku-band (12-18 ghz) mixer design in tsmc 0.18 µm is presented. this mixer has high linearity a...
Multi-threshold voltage CMOS (MTCMOS) is the most widely used circuit technique for suppressing the subthreshold leakage currents in idle circuits. When a conventional sequential MTCMOS circuit transitions from the sleep mode to the active mode, signi ̄cant bouncing noise is produced on the power and ground distribution networks. The reliability of the surrounding active circuitry is seriously d...
In this work, we have used a statistical simulation based approach to predict variability in the noise margins of 6T SRAM cell caused by Random Dopant Fluctuation (RDF) for a well scaled 35 nm technology. Impact of RDF on Static Noise Margin (SNM) as well as Dynamic Noise Margin (DNM) has been investigated. Results show that RDF will result in up to 45% variability in SNM and DNM. This variabil...
An SoC with ARM® CortexTM-M0 CPU cores and SRAMs is implemented in both 65nm baseline and Deeply Depleted ChannelTM (DDC) technologies. DDC technology demonstrates more than 50% active and static power reduction for the CPU cores at matched 350 MHz speed via VDD scaling and body biasing. Alternatively, DDC technology demonstrates 35% speed increase at matched power. The results hold across proc...
In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic op...
نمودار تعداد نتایج جستجو در هر سال
با کلیک روی نمودار نتایج را به سال انتشار فیلتر کنید