reconfigurable instruction set processors allow customization for an application domain by extending the core instruction set architecture. extracting appropriate custom instructions is an important phase for implementing an application on a reconfigurable instruction set processor. a custom instruction (ci) is usually extracted from critical portions of applications and implemented on a reconf...

DRAMSys: A flexible DRAM Subsystem Design Space Exploration Framework Methodology for Rapid Accelerator Development Applied to Financial Applications A Reconfigurable Application Specific Instruction Set Processor. Adaptive processor architecture invited paperMichael Hübner, Diana Göhringer, Carsten Tradowsky, Jörg KAHRISMA: A novel Hypermorphic Reconfigurable-Instruction-Set Cross-architectura...

Design of a programmable Multi core processor to implement compute several complex multimedia applications is presented. The Processor is expected to complete the given task with minimum latency. The hardware must adhere to minimal area and power requirements. This paper gives design details for enhancement of performance parameters of multi core processors. It is necessary to optimize the proc...

Reconfigurable instruction set processors have the capability to adapt their instruction sets to the application being executed through a reconfiguration in their hardware. Through this adaptation, they are expected to achieve a great improvement in performance compared to fixed instruction set processors. In this paper, we discuss the different hardware aspects that have to be considered durin...

Reconfigurable instruction set processors allow customization for an application domain by extending the core instruction set architecture. Extracting appropriate custom instructions is an important phase for implementing an application on a reconfigurable instruction set processor. A custom instruction (CI) is usually extracted from critical portions of applications and implemented on a reconf...

Modern embedded systems have an emerging demand on high performance and low power circuits. Traditionally special functional units for each application are developed separately. These are plugged to a general purpose processors to extend its instruction set making it an application specific instruction set processor. As this strategy reaches its boundaries in area and complexity reconfigurable ...

We propose a dynamically reconfigurable arithmetic block architecture for customizing embedded application processor instruction sets. Our architecture uses medium-grained arithmetic blocks and a dedicated but reconfigurable interconnection network to support a wide range of instruction-set extensions. Our experimental results demonstrate the performance of our arithmetic block compared to a ge...

A class of reconfigurable processors is introduced in which support for an instruction set is distributed among a collection of pre-defined configurations. For this new class of reconfigurable processors, there is assumed to be a pre-defined collection of configurations in which each configuration supports a subset of the overall instruction set. The union of all subsets of instructions, associ...

This paper describes an approach for adaptive dynamic instruction set extension, tuning processors to specific applications. These new instructions are generated after production. The processor has two modes: training mode and normal mode. The application-specific instructions are extracted from the critical portions of the code detected by a profiler at training mode. At normal mode they are e...