This paper presents power analysis of the full adder cells reported as having a low PDP (Power Delay Product), by means of speed, power consumption and area. These full adders were designed upon various logic styles to derive the sum and carry outputs. Two new high-speed and low-power full adder cells designed with an alternative internal logic structure and pass-transistor logic styles that le...

full adder cell is often placed in the critical path of other circuits. therefore it plays an important role in determining the entire performance of digital system. moreover, portable electronic systems rely on battery and low-power design is another concern. in conclusion it is a vital task to design high-performance and low-power full adder cells. since delay opposes against power consumptio...

   Nowadays, the portable multimedia electronic devices, which employ signal-processing modules, require power aware structures more than ever. For the applications associating with human senses, approximate arithmetic circuits can be considered to improve performance and power efficiency. On the other hand, scaling has led to some limitations in performance of nanoscale circuits. According...

This paper introduces a new design of penternary inverter gate based on graphene nanoribbon field effect transistor (GNRFET). The penternary logic is one of Multiple-valued logic (MVL) circuits which are the best substitute for binary logic because of its low power-delay product (PDP) resulting from reduced complexity of interconnects and chip area. GNRFET is preferred over Si-MOSFET for circui...

For digital circuits with ultra-low power consumption, floating-gate circuits have been considered to be a technique potentially better than standard static CMOS circuits. By having a DC offset on the floating gates, the effective threshold voltage of the floating-gate transistor is adjusted and the speed and power performance can be altered. In this paper the basic performance related properti...

In this paper, the various low power delay product full adder circuits have been analyzed. The adder is the fundamental blocks of any arithmetic circuit, so even a small reduction power or delay leads to improved performance of the circuit with optimal power saving. A 10T adder technique is the famous low power delay product full adder circuits with minimum transistor count. A new 10T technique...

In this paper, the performance of a CNT-JLTFET under different values of torsional strains of 0, 3, and 5 degrees has been investigated. Simulation has been carried out using non-equilibrium Green’s function (NEGF) formalism in the mode-space approach and in the ballistic limit. The simulation results indicate that, under torsional strain, an increase occurs in the energy band-gap, and thus the...