we design and simulate a five-port optical router, which is composed of twenty mach-zehnder-based switching elements and twelve waveguide crossings for use in integrated photonic interconnection networks. we simulated and analyzed the operation of the proposed optical router from the aspects of insertion loss, power budget, q-factor and the minimum bit error ratio by use of optisystem simulator...

For the first time, the 4- and 5-port optical routers are designed by using the West First routing algorithm for use in optical network on chip. The use of the WF algorithm has made the designed routers to provide non-blocking routing in photonic network on chip. These routers not only are based on high speed Mach-Zehnder switches(Which have a higher bandwidth and more thermal tolerance than mi...

For the first time, the 4- and 5-port optical routers are designed by using the West First routing algorithm for use in optical network on chip. The use of the WF algorithm has made the designed routers to provide non-blocking routing in photonic network on chip. These routers not only are based on high speed Mach-Zehnder switches(Which have a higher bandwidth and more thermal tolerance than mi...

Nowadays, increasing emerging application complexity and improvement in process technology have enabled the design of many-core processors with tens to hundreds of cores on a single chip. Photonic Network-on-Chips (PNoCs) have recently been proposed as an alternative approach with high performance-per-watt characteristics for intra-chip communication. In this thesis, we present a performance ex...

nowadays network-on-chips is used instead of system-on-chips for better performance. this paper presents a new algorithm to find a shorter path, and shows that genetic algorithm is a potential technique for solving routing problem for mesh topology in on-chip-network.

As high-performance processors move towards multicore architectures, packet-switched on-chip networks are gaining wide acceptance as interconnect solutions that can directly address the bandwidth and latency requirements as well as provide partial relief to the broader challenge of power dissipation. Still, studies show that the power consumed by on-chip networks will remain a major issue that ...

as technology scales deep into the nanometer regime, on-chip communication becomes more susceptible to transient noise sources, such as crosstalk, external radiation, and spurious voltage spikes. the network on chip s modularity and reusability has brought about the use of error control methods to address transient errors in network on chip links.in this work, we design a fault tolerance router...

Due to the increasing growth of processing cores in complex computational systems, all the connection converted bottleneck for all systems. With the protection of progressing and constructing complex photonic connection on chip, optical data transmission is the best choice for replacing with electrical interconnection for the reason of gathering connection with a high bandwidth and insertion lo...

1. Introduction Much recent progress in silicon nanophotonic technology has enabled the prospect of high-performance nano-photonic networks-on-chip (NoCs), which have become very attractive solutions to the growing bandwidth and power consumption challenges of future high-performance chip multiprocessors [1–4]. The design of our high-performance nanophotonic NoC commences at the individual sili...