Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the perform...

this paper proposes a new method for parameter estimation of distorted single phase signals, through an improved demodulation-based phase tracking incorporated with a frequency adaptation mechanism. the simulation results demonstrate the superiority of the proposed method compared to the conventional sogi (second-order generalized integrator)-based approach, in spite of the dc-offset and harmon...

the aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. for this purpose, first, an exact mathematical model of phase locked loop (pll) based frequency synthesizer is described and analyzed. then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. based on this formula, the phase ...

This work concerns with the design and analysis of phase locked loops (PLLs). In the last decade a lot of works have been done about the analysis of PLLs. The phase locked loops are analyzed briefly, second order, third order, and fourth order. In practically the design of 1.3 GHz, 1.9V second order PLL is considered. SPICE simulation program results confirm the theory. Key-Words: Phase Locked ...

This paper presents a review of phase locked loop (PLL) techniques. The different types of phase detector, loop filter and oscillators are discussed. It alleviates the problems associated with the classical analog PLL. Linear PLL, Digital PLL and All digital PLL models are implemented in Simulink Simulation results in Simulink gives the performance overview of the three types of PLL. Keywords— ...

The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase ...

An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm and consumes 88 μW at 0.4-V supply for...