نتایج جستجو برای: phase locked loop pll
تعداد نتایج: 726850 فیلتر نتایج به سال:
a phase-locked loop (pll) based frequency synthesizer is an important circuit that is used in many applications, especially in communication systems such as ethernet receivers, disk drive read/write channels, digital mobile receivers, high-speed memory interfaces, system clock recovery and wireless communication system. other than requiring good signal purity such as low phase noise and low spu...
Abstract— This paper presents a novel approach to obtain fast locking PLL by embedding a nonlinear element in the loop of PLL. The nonlinear element has a general parametric Taylor expansion. Using genetic algorithm (GA) we try to optimize the nonlinear element parameters. Embedding optimized nonlinear element in the loop shows enhancements in speed and stability of PLL. To evaluate the perform...
this paper proposes a new method for parameter estimation of distorted single phase signals, through an improved demodulation-based phase tracking incorporated with a frequency adaptation mechanism. the simulation results demonstrate the superiority of the proposed method compared to the conventional sogi (second-order generalized integrator)-based approach, in spite of the dc-offset and harmon...
the aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. for this purpose, first, an exact mathematical model of phase locked loop (pll) based frequency synthesizer is described and analyzed. then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. based on this formula, the phase ...
This work concerns with the design and analysis of phase locked loops (PLLs). In the last decade a lot of works have been done about the analysis of PLLs. The phase locked loops are analyzed briefly, second order, third order, and fourth order. In practically the design of 1.3 GHz, 1.9V second order PLL is considered. SPICE simulation program results confirm the theory. Key-Words: Phase Locked ...
در این پایان نامه یک سنتز کننده فرکانسی (به همراه vco ) با توان مصرفی پایین و فرکانس کاری 2.4ghz به عنوان اسیلاتور محلی برای استفاده در گره wsn منطبق بر استاندارد ieee802.15.4/zigbee ارائه شده است. برای کاهش توان مصرفی و هزینه ساخت، سنتز کننده فرکانسی از نوعinteger-n pll (phase locked loop) انتخاب شده است. همچنین یک بلوک شکل دهنده موجی جدید برای استفاده در مدولاتور oqpsk طراحی و پیاده سازی شده ...
This paper presents a review of phase locked loop (PLL) techniques. The different types of phase detector, loop filter and oscillators are discussed. It alleviates the problems associated with the classical analog PLL. Linear PLL, Digital PLL and All digital PLL models are implemented in Simulink Simulation results in Simulink gives the performance overview of the three types of PLL. Keywords— ...
طراحی PLL دو حلقه ای مبتنی بر آشکارسازی فاز پنجره‌ای با سرعت قفل بالا، توان مصرفی و اسپور مرجع پایین
In this paper, a dual loop PLL with short locking time, low power consumption and low reference spur is presented. The output frequency and reference frequency of the designed circuit are 3.2 GHz and 50 MHz, respectively, aimed to WiMAX applications. In the proposed circuit in locked state, some parts of the circuit could be powered off, to reduce overall power consumption. Phase detection in t...
The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase ...
An ultra-low voltage phase-locked loop (PLL) is demonstrated in standard 130-nm CMOS technology. The PLL employs a novel low-voltage charge-pump circuit which compensates current and leakage mismatches that result in suppressed reference spurs. Its voltage-controlled oscillator is realized with supply-regulated active-loop filter. Our PLL occupies 0.014 mm and consumes 88 μW at 0.4-V supply for...
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