نتایج جستجو برای: optimized input voltage
تعداد نتایج: 406817 فیلتر نتایج به سال:
this paper presents the method of reducing torque ripple of brushless dc (bldc) motor. the commutation torque ripple is reduced by control of the dc link voltage during the commutation time. the magnitude of voltage and commutation time is estimated by a neural network and optimized with an optimization method named particle swarm optimization (pso) algorithm analysis. the goal of optimization ...
this thesis is presented 10 ghz voltage controlled ring oscillator for high speed application. the voltage controlled ring oscillator was designed and fabricated in 0.13یm cmos technology. the oscillator is 7-stages ring oscillator with one inverter replaced by nand-gate for shutting down in the ring oscillator during idle mode. tri-state inverter was used to control of 126 bit vector in ri...
in this thesis,spin dependend transport and electron transport through of ng/sg(graphene/ superconductor graphen) are studied in the junction of ng/fgt/sg. due to andreev reflection conductance increases in the presence of superconductor graphene.also, by applying a voltage gate on a superconductor, fermi level shifts and the conductance is independent of ferromagnatic substrate. also, the cond...
a phase-locked loop (pll) based frequency synthesizer is an important circuit that is used in many applications, especially in communication systems such as ethernet receivers, disk drive read/write channels, digital mobile receivers, high-speed memory interfaces, system clock recovery and wireless communication system. other than requiring good signal purity such as low phase noise and low spu...
A cascode LNA was optimized for a GPS receiver radio frequency front end using a 0.18 μm CMOS technology. By careful choice of device geometry, gate and source degeneration inductors, a fully integrated LNA can be optimized to have a low noise figure, a high voltage gain and a wide dynamic range. The optimized LNA has a 1.512 dB noise figure, a –42.05 dB S11, a 20.04 dB voltage gain a –19.82 dB...
This paper presents the method of reducing torque ripple of brushless DC (BLDC) motor. The commutation torque ripple is reduced by control of the DC link voltage during the commutation time. The magnitude of voltage and commutation time is estimated by a neural network and optimized with an optimization method named particle swarm optimization (PSO) algorithm analysis. The goal of optimizati...
The current-fed dual active bridge (CF-DAB) dc–dc converter gains growing applications in photovoltaic (PV) and energy storage systems due to its advantages, e.g., a wide input voltage range, a high step-up ratio, a low input current ripple, and a multiport interface capability. In addition, the direct input current controllability and extra control freedom of the CF-DAB converter make it possi...
A design model to find the optimized device dimensions and layout spacings on the input ESD clamp devices is developed in this work to keep the total input capacitance almost constant, even if the analog signal has a varying input voltage. An analog ESD protection circuit has been designed to solve ESD protection challenge on the analog pins for highfrequency applications. The device dimension ...
this paper presents a detailed small-signal and transient analysis of a full bridge pwm dc-dc converter designed for high voltage, high power applications using an average model. the derived model is implemented in a typical system and used to produce the small-signal and transient characteristics of the converter. results obtained in the analysis of the high voltage and high power design examp...
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