One of the foremost vital problems in communication customary is that the secure transport protocols. This paper can offer a doable resolution for Rijindael’s encryption and decoding algorithmic program using NIOS II processor, provided by ALTERA to be enforced in FPGA. We are going to see the performance of Rijindael’s AES using NIOS II/e (economic), NIOS II/s (standard) and NIOS II/f (fast). ...

as functional integration has increased in hand-held consumer devices features such as global positioning system (gps) receivers have been embedded in increasingly more devices in recent years. for example, the train positioning system based on gps provides an integrated positioning solution which can be used in many rail applications without a cost intensive infrastructure. the network built i...

A heterogeneous multi-valued decision diagram of encoded characteristic function for nonzero outputs (HMDD for ECFN) represents a multioutput logic function efficiently. As for the speed, the HMDD for ECFN machine is 3.02 times faster than the Core i5 processor, and is 12.50 times faster than the Nios II processor. As for the power-delay product, it is 32.72 times lower than the Core i5 process...

<p>This paper presents an FPGA image segmentation-binarization system based on<em> </em>Iterative Self Organizing DATA <em>(ISODATA)</em> threshold using histogram analysis for embedded systems. The module computes pixels levels statistics which are used by the ISODATA algorithm to determine segmentation threshold. In our case, this binarizes a gray-scale into two ...

As functional integration has increased in hand-held consumer devices features such as Global Positioning System (GPS) receivers have been embedded in increasingly more devices in recent years. For example, the train positioning system based on GPS provides an integrated positioning solution which can be used in many rail applications without a cost intensive infrastructure. The network built i...

digital watermarking techniques have been exploited to protect the copyright of multimedia data in the emerging systems. In this paper, an efficient watermarking approach for System-on-Programmable-Chip (SOPC) realization is proposed. We analyzed the software efficiency of watermark embedding with Nios-II soft-CPU and proposed a cost-effective architecture for the design of Discrete Cosine Tran...

CRC is significantly more efficient in hardware than software; consequently, you can improve the throughput of your system by implementing a hardware accelerator for CRC. In addition, by eliminating CRC from the tasks that the processor must run, the processor has more bandwidth to accomplish other tasks. Figure 8–1 illustrates a system in which a Nios® II processor offloads CRC processing to a...

The System-on-Programmable-Chip (SoPC) architecture to implement a stereo matching algorithm based on the sum of absolute differences (SAD) in a FPGA chip is proposed. The hardware implementation involves a 32-bit Nios II microprocessor, memory interfaces and stereo matching algorithm circuit module. The Nios II microprocessor is a configurable soft IP core in charge of managing the buffer of t...