Neural algorithms and architectures are rarely tested on actual hardware testbeds owing to the high cost and long time required to develop neural chips. A Fast Prototyping Neural System FPNS where neural architectures can be easily programmed and conngured on programmable chips is here presented. Two diierent case studies were developed and used as benchmark for our system, showing a good perfo...

Two novel neural chips SAND (Simple Applicable Neural Device) and SIOP (Serial Input Operating Parallel) are described. Both are highly usable for hardware triggers in particle physics. The chips are optimized for a high input data rate at a very low cost basis. The performance of a single SAND chip is 200 MOPS due to four parallel 16 bit multipliers and 40 bit adders working in one clock cycle...

Results from a non-leptonic neural-network trigger hosted by experiment WA92, looking for beauty particle production from 350 GeV negative pions on a fixed Cu target, are presented. The neural trigger has been used to send events selected by means of a non-leptonic signature based on microvertex detector information to a special data stream, meant for early analysis. The non-leptonic signature,...

An analog CMOS chip set for implementations of artificial neural networks (ANNs) has been fabricated and tested. The chip set consists of two cascadable chips: a neuron chip and a synapse chip. Neurons on the neuron chips can be interconnected at random via synapses on the synapse chips thus implementing an ANN with arbitrary topology. The neuron test chip contains an array of 4 neurons with we...

This paper presents a systematic approach to design CMOS chips with concurrent picture acquisition and processing capabilities. These chips consist of regular arrangements of elementary units, called smart pixels. Light detection is made with vertical CMOSBJTs connected in a Darlington structure. Pixel smartness is achieved by exploiting the Cellular Neural Network paradigm [1], [2], incorporat...

Two ANNA neural-network chips are integrated on a 6U VME board, to serve as a high-speed platform for a wide variety of algorithms used in neural-network applications as well as in image analysis. The system can implement neural networks of variable sizes and architectures, but can also be used for filtering and feature extraction tasks that are based on convolutions. The board contains a contr...

Conclusions: In this Letter, a new modular analogue neuro-chip set with an on-chip learning capability is presented for adaptive nonlinear equalisers. Using the analogue neural equaliser, digital telecommunication receivers do not need, and can eliminate, supplementary devices such as analogue-to-digital converters and digital equalisers. Although several chips are used for experiments, one-chi...

A programmable cellular neural network has been designed in a 0.8μ CMOS technology. An arbitrarily large analog CNN can be constructed by modularly connecting ‘tile’ CNN chips, each with a modest number of cells. The network operates in continuous time, has a PWL output function, and the cell connections (template values) are realized as sets of switchable unit and half-unit transconductors. Ma...