fab-less business model in semiconductor industry has led to serious concerns about trustworthy hardware. in untrusted foundries and manufacturing companies, submitted layout may be analyzed and reverse engineered to steal the information of a design or insert malicious trojans. understanding the netlist topology is the ultimate goal of the reverse engineering process. in this paper, we propose...

Fab-less business model in semiconductor industry has led to serious concerns about trustworthy hardware. In untrusted foundries and manufacturing companies, submitted layout may be analyzed and reverse engineered to steal the information of a design or insert malicious Trojans. Understanding the netlist topology is the ultimate goal of the reverse engineering process. In this paper, we propose...

Fab-less business model in semiconductor industry has led to serious concerns about trustworthy hardware. In untrusted foundries and manufacturing companies, submitted layout may be analyzed and reverse engineered to steal the information of a design or insert malicious Trojans. Understanding the netlist topology is the ultimate goal of the reverse engineering process. In this paper, we propose...

In this paper, a hardware implementation of the AES128 encryption algorithm is proposed. A unique feature of the proposed pipelined design is that the round keys, which are consumed during different iterations of encryption, are generated in parallel with the encryption process. This lowers the delay associated with each round of encryption and reduces the overall encryption delay of a plaintex...

Network data is, currently, often encrypted at a low level. In addition, as it is widely supported, the majority of future networks will use low-layer (IP level) encryption. Moreover, current trends imply that future networks are likely to be dominated by mobile terminals, thus, the power consumption and electromagnetic emissions aspects of encryption devices will be critical. This paper presen...

Phased logic is a synthesis/mapping methodology that allows a standard clocked netlist (combinational gates + DFFs) to be automatically mapped to a non-clocked netlist that uses special gates called phased logic gates. The new netlist has no clock networks and the only required global signal is a power-on reset. We demonstrate the viability of the phased logic approach via the synthesis and sim...

graph G and applying the eigenvector technique of Barnes 111 to partition the graph G into IC blocks of fixed module . size. An efficient generalization of the Fiduccia-Mattheyses node interchange heuristic is developed to further reduce the number of nets connecting k blocks [3]. This node interchange heuristic is tested on the one resulting netlist partition obtained by this new eigenvector a...

A fast eigenvector technique for obtaining good initial node partitions of netlists for use in interchange heuristics is described. The method is based on approximating the netlist or hypergraph by a weighted graph, G, such that the sum of the cut edges in G tightly underestimates the number of cut nets in any netlist partition. An eigenvector technique of Barnes [2] is used to partition the gr...