Leakage current is an important qualitative metric of LSI (Large Scale Integrated circuit). In this paper, we focus on reduction of leakage current variation under the process variation. Firstly, we derive a set of quadratic equations to evaluate delay and leakage current under the process variation. Using these equations, we discuss the cases of varying leakage current without degrading delay ...

Gate oxide tunneling current (Igate) will become the dominant component of leakage in CMOS circuits as the physical oxide thickness (Tox) goes below 15Å. Increasing the value of Tox reduces the leakage at the expense of an increase in delay, and a practical tradeoff between delay and leakage can be achieved by assigning one of the two permissible Tox values to each transistor. In this paper, we...

We study ultrabroadband slow light in a warm rubidium vapor cell. By working between the D1 and D2 transitions, we find a several-nanometer window centered at 788:4 nm in which the group index is highly uniform and the absorption is small (<1%). We demonstrate that we can control the group delay by varying the temperature of the cell, and we observe a tunable fractional delay of 18 for pulses a...

This paper presents an ultra-wide-range all-digital delaylocked loop (DLL). The proposed DLL uses a novel delay circuit which uses the transistor’s leakage current in advanced CMOS process to generate a very large propagation delay. Thus, the proposed DLL can operate at very low frequency with small chip area and low power consumption. The proposed DLL can operate from 600 kHz to 1.2GHz in the ...

In this paper, the novel “tapered-Vth” approach to design energy-efficient CMOS buffers is introduced. In this approach, the substantial energy consumption due to leakage is reduced by tapering the threshold voltage throughout the buffer stages, other than tapering the transistor size. More specifically, the threshold voltage is progressively reduced when going from the last to the first stage....

The paper is concerned with robust stability criteria for Takagi- Sugeno (T-S) fuzzy systems with distributed delays and time delay in the leakage term. By exploiting a model transformation, the system is converted to one of the neutral delay system. Global robust stability result is proposed by a new Lyapunov-Krasovskii functional which takes into account the range of delay and by making use o...

This paper deals with the performance of the fractional delay estimator in the joint complex amplitude/delay estimation algorithm dedicated to digital Tx leakage compensation in FDD transceivers. Such transceivers suffer from transmitter-receiver signal leakage. Combined with non linearity of components in the receiver path, the baseband received signal is impaired by a baseband polluting signa...

the paper is concerned with robust stability criteria for takagi- sugeno (t-s) fuzzy systems with distributed delays and time delay in the leakage term. by exploiting a model transformation, the system is converted to one of the neutral delay system. global robust stability result is proposed by a new lyapunov-krasovskii functional which takes into account the range of delay and by making use o...

When working for low power application the main estimation is to reduce leakage components and parameters. This stanza explores a vast link towards low leakage power SRAM cells using new technology and devices. The RAM contains bi-stable cross coupled latch which has V_th higher in write mode access MOSFET (Metal Oxide Semiconductor Field Effect Transistor) and lower V_th in read access mode MO...