the performance of nanoscale field effect diodes as a function of the spacer length between two gates is investigated. our numerical results show that the ion/ioff ratio which is a significant parameter in digital application can be varied from 101 to 104 for s-fed as the spacer length between two gates increases whereas this ratio is approximately constant for m-fed. the high-frequency perform...

The performance of nanoscale Field Effect Diodes as a function of the spacer length between two gates is investigated. Our numerical results show that the Ion/Ioff ratio which is a significant parameter in digital application can be varied from 101 to 104 for S-FED as the spacer length between two gates increases whereas this ratio is approximately constant for M-FED. The high-frequency perform...

abstract: this paper is the first study on the impact of ambient temperature on the electrical characteristics and high frequency performances of double gate armchair graphene nanoribbon field effect transistor (gnrfet). the results illustrate that the gnrfet under high temperature (ht-gnrfet) has the highest cut-off frequency, lowest sub-threshold swing, lowest intrinsic delay and power delay ...

With submicron technologies, gate delays are dominated by gate load delays rather than intrinsic gate delays. While the common approach for computing gate load delay (or total gate delay) is through delay tables (or k-factor equations), there are important methodology problems associated with the delay table approach. In this paper, we propose a gate driver model with a Thevenin equivalent circ...

Precise delay generation is a necessity in state-of-the-art integrated test and measurement chips[ll. High time resolution is difficult to achieve. It requires precise delays significantly smaller than an intrinsic gate delay. Precise delays with gate-delay resolution can be achieved by phase locking a ring oscillator to an established clock. An array oscillator, a series of coupled ring oscill...

In this paper, the transient device performance analysis of n-type Gate Inside JunctionLess Transistor (GI-JLT) has been evaluated. 3-D Bohm Quantum Potential (BQP) transport device simulation has been used to evaluate the delay and power dissipation performance. GI-JLT has a number of desirable device parameters such as reduced propagation delay, dynamic power dissipation, power and delay prod...

A vertically integrated alternative for integrated injection logic has been realized, named buried injector logic (BIL). 1 MeV ion implantations are used to create buried layers. The vertical pnp and npn transistors have thin base regions and exhibit a limited charge accumulation if a gate is saturated. d.c. and dynamic analysis of BIL-gate behaviour are given. A minimum gate delay of well belo...

This study introduces a reversible optical fulladder. Also optical NOT and NOR gates are implemented through Electro-Absorption-Modulator / Photo Detector (EAM/PD) pairs, were utilized for fulfilling reversible R gate. Then, reversible fulladder was designed based on the proposed reversible optical R gate. The operation of the suggested fulladder was simulated using Optispice and it was fou...