In this paper we propose a practical approach for on-chip inductance extraction. This approach differs from previous methods in that it uses circuit characteristics to obtain a sparse, stable and symmetric inductance matrix, using the concept of resistance dominant and inductance dominant lines. Experimental results show that only the important inductance terms related to strong inductance coup...

Abstract: For high-speed circuits, on-chip inductance can no longer be ignored. This paper deals with inductance in the presence of multi-layered meshes used for on-chip power supplies. We have shown ways of designing power/ground (p/g) mesh that reduce inductance. Accurate 3-dimensional inductance extraction problem is intractable for large chips. We have demonstrated the feasibility of using ...

Based on product related scenarios, the impact of on-chip inductance on power supply integrity is analyzed. The impact of varying current profiles is shown to be minimal. In a regular power grid with regular bump connections, the impact of on-chip inductance on the cycle average of the supply voltage can be neglected, even for a worst case estimation of on-chip inductance. Whereas, the maximum ...

We have studied the kinetic inductance fraction (ratio of kinetic inductance to total inductance) of superconducting coplanar waveguides (CPWs) by measuring the resonance frequency of CPW transmission line resonators. We describe a procedure for accurately determining the kinetic inductance of transmission line geometries with small kinetic inductance fractions. In this approach, we compare the...

Universidad Autónoma de Zacatecas 13.1 Equivalent Circuit ........................................................... 13-1 13.2 Resistance ......................................................................... 13-2 Frequency Effect . Temperature Effect . Spiraling and Bundle Conductor Effect 13.3 Current-Carrying Capacity (Ampacity) ........................ 13-5 13.4 Inductance and Inductive...

A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip interconnect delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance. A test c...

Abstract: In order to increase the power rating of electric vehicles, insulated gate bipolar translator (IGBT) modules with multiple power terminals are usually adopted. The transient current sharing of the same polarity power terminals is related to the stray inductance in the branches of the bus-bar. Based on the laminated bus-bar of a three-phase inverter in the electric vehicles that consis...

On-chip inductance extraction and analysis is becoming increasing critical. Inductance extraction can be difficult, cumbersome and impractical on large designs as inductance depends on the current return path — which is typically unknown prior to extracting and simulating the circuit model. In this paper, we propose a new circuit element, K, to model inductance effects, at the same time being e...

An analytical procedure for the calculation of the inductance of planar zig-zag spiral inductors is proposed. The procedure is based on the partial inductance concept and models the inductor as a series of a number of parts. The self-inductance of each individual part, which has the shape of a parallelogram, and the mutual inductance between any two parts of the inductor are determined. The ind...