the aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. for this purpose, first, an exact mathematical model of phase locked loop (pll) based frequency synthesizer is described and analyzed. then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. based on this formula, the phase ...

The aim of this paper is to minimize output phase noise for the pure signal synthesis in the frequency synthesizers. For this purpose, first, an exact mathematical model of phase locked loop (PLL) based frequency synthesizer is described and analyzed. Then, an exact closed-form formula in terms of synthesizer bandwidth and total output phase noise is extracted. Based on this formula, the phase ...

A frequency synthesizer employing a new digitalfrequency measurement method in a feedback loop is described. The synthesizer features high-frequency resolution and a high operating frequency. The mostly digital nature of the synthesizer and relaxed voltage-controlled oscillator requirements also make the synthesizer suitable for integration. Models for the synthesizer are developed and experime...

Title: Frequency synthesis for cognitive multi-radio

In this paper, we propose a speedup method of frequency switching time in the phase locked loop (PLL) frequency synthesizer using the target frequency detector (TFD). The TFD detects the time Ta for any channels where the output of the PLL frequency synthesizer reaches the target frequency for the first time. At Ta, the programmable divider, the reference divider and the phase comparator are re...

This paper present a new technique in digital waveform synthesizers based on the use of the first quadrant in order to present the other three quarters. This will reduce the size of the memory locations to the quarter, and increase the number of samples per period four times in comparison with the full wave synthesizer.