In the phase locked loop (PLL) frequency synthesizer which is used in a higher frequency region, the prescaler method is employed in order to increase the operating frequency of the programmable divider. However, since the fixed divider whose division ratio is same as the prescaler is installed at the following stage of the reference divider, the reference frequency is decreased and the perform...

Introduction: Fractional-N frequency dividers allow PLL Synthesizers to have frequency resolutions finer than the reference frequency. However, there are two disadvantages in a fractional-N divider, namely, fractional spurs generation and frequency range limitation. A fractional-N divider generates fractional spurs due to the fixed pattern of the dual-modulus divider [1]. The frequency range of...

A high-speed low power scalable programmable dual modulus digital CMOS frequency divider architecture is proposed. The unique frequency divider architecture includes a high speed parallel counter with State Excitation Module, a switchover trigger circuit, a modulus switchover circuit and a reloader circuit. The mode switchover circuit has two sets of external programmable inputs for two alterna...

This paper presents a broadband high operating frequency divide-by-2 frequency divider. This divider uses sourcecoupled logic (SCL) with two static loading master-slave D latches which achieves high input operating frequency, high input sensitivity and low power dissipation. This divider can work from 8GHz~ 27GHz and the input power is -40dBm@18GHz. The chip area is 735μm×480μm with only 4.6mW ...

In this paper, the divider circuit for PLL based Frequency Synthesizer has been designed. In the divider circuit, three types of counters have been used namely Prescaler, Main Counter and Swallow Counter. The Divider circuit is a two modulus Divider and it can be used to divide by any value in the range 4635 to 4650 as per the requirement. It uses a two modulus Prescaler and it has two modes of...

The objective of this project is to develop a Programmable Frequency divider design for multi GHz PLL System implementation on FPGA using VHDL (hardware description language). The frequency divider architecture features 6 parallel divider chains, each one of them implementing a single division ratio. The desired frequency division ratio is then selected using the four control bits of an output ...

An ultra-low power injection locked frequency divider (ILFD) is presented and demonstrated. Based on a 5-stage single ended ring oscillator, the ILFD achieves a lock range of 56% at a division ratio of 5 in the medical implant communications service (MICS) and the 433MHz ISM frequency bands. The ILFD is implemented in a 90nm CMOS process. It consumes 3 μW of power from a 1.0V supply and 100 μm ...

Filter plays an important role in communication systems. It is an electronic device that allows signal in certain frequency ranges to go through. In other words, filter helps remove all the unwanted frequency components in a signal. Generally, there are four types of filters: lowpass filter, highpass filter, bandpass filter and bandstop filter. Two filters have been proposed in my project. The ...

The behavior of two frequency divider circuits using negative differential resistance (NDR) circuit is studied. This NDR circuit is made of three resistors (R) and two bipolar-junction-transistor (BJT) devices. It can show the NDR characteristic in its current-voltage curve by suitably designing the resistances. We discuss a dynamic frequency divider, which is made of a R-BJT-NDR circuit, an in...