many real world problems can be modelled as an optimization problem. evolutionary algorithms are used to solve these problems. ant colony algorithm is a class of evolutionary algorithms that have been inspired of some specific ants looking for food in the nature. these ants leave trail pheromone on the ground to mark good ways that can be followed by other members of the group. ant colony optim...

Placement process is one of the vital stages in physical design. In this stage, modules and elements of circuit are placed in distinct locations according to optimization basis. So that, each placement process tries to influence on one or more optimization factor. In the other hand, it can be told unequivocally that FPGA is one of the most important and applicable devices in our electronic worl...

Ultra-Fast Automatic Placement for FPGAs The demand for high-speed Field-Programmable Gate Array (FPGA) compilation tools has escalated for three reasons: first, as FPGA device capacity has grown, the computation time devoted to placement and routing of circuits has grown more dramatically than the available computer power. Second, there exists a subset of users who are willing to accept a redu...

In this paper we describe Frontier, an FPGA placement system that uses design macro-blocks in conjuction with a series of placement algorithms to achieve highly-routable and high-performance layouts quickly. In the first stage of design placement, a macro-based floorplanner is used to quickly identify an initial layout based on inter-macro connectivity. Next, an FPGA routability metric, previou...

As a good trade-off between CPU and ASIC, FPGA is becoming more widely used in both industry and academia. The increasing complexity and scale of modern FPGA, however, impose great challenges on the FPGA placement and packing problem. In this paper, we propose RippleFPGA to solve the packing and placement simultaneously through a set of novel techniques, such as (i) smooth stair-step flow, (ii)...

In this paper, we propose a fast placer for FPGA placement on a new commercial hierarchical FPGA device. The novelty of this research lies in the application of a multilevel V-shape optimization flow including an architecture related cluster process and a constructive placement. The new placer can handle large-scale FPGA placement problem quickly. Experimental results show that the proposed pla...

Because of the more restrictive placement and routing constraints in Xilinx FPGA designs, conventional physical design tools for general placement and routing architectures usually do not work well for FPGA designs. Moreover, to generate high quality circuits which are easy to place and route, it is important to consider the specific physical design constraints during the technology mapping pro...

Due to advancement in reconfigurable computing, Field Programmable Gate Array (FPGA) has gained significance due to its low cost and fast prototyping. Parallelism, specialization, and hardware level adaptation, are the key features of reconfigurable computing. FPGA is a programmable chip that can be configured or reconfigured by the designer, to implement any digital circuit. One major challeng...

Placement (and routing) of circuits is very computationally intensive. This intensity has motivated several attempts at acceleration of this process for application-specific integrated circuits (ASIC) and Field-programmable gate arrays (FPGA). In this paper an overview of some of these attempts is given. Specifically, parallelization of the standard simulated annealing (SA) algorithm is examine...

Modern field-programmable gate array (FPGA) devices contain complex clock architectures on top of configurable logics. Unlike application specific integrated circuits (ASICs), the physical structure of clock networks in an FPGA is pre-manufactured and cannot be adjusted to different applications. Furthermore, clock routing resources are typically limited for high-utilization designs. Consequent...