Floorplanning is an important physical design step for hierarchical, building-block design methodology. When the circuit size get increases the complexity of the circuit also increases. To deal with the increasing design complexity the intellectual property (IP) modules are mostly used in floorplanning. This paper presents a Hybrid particle swarm optimization algorithm for floorplanning optimiz...

-Fixed-outline floorplanning enables multilevel hierarchical design, where aspect ratios and area of floorplans are usually imposed by higher level floorplanning and must be satisfied. Simulated Annealing is widely used in the floorplanning problem. It is well-known that the solution space, solution perturbation, and objective function are very important for Simulated Annealing. In this paper, ...

As transistors scale, system temperatures are rising, and with them, cooling costs. Faced with such challenges, designers have developed a variety of techniques to reduce temperatures at design-time, through floorplanning, and at run-time, using dynamic thermal management. Multi-core floorplanning, in particular, presents unique opportunities for temperature management: for example, cores can b...

Floorplanning determines the positions of blocks on a chip subject to various objectives. In practical physical design, on the requirement of placing some blocks along the boundaries of the chip such as the blocks can be connected to I/O pads, the floorplanning with boundary constraint is raised. In this paper, we apply a floorplanning algorithm named area predicted transitive closure graphs (A...

With resent advances of Deep Sub Micron technologies, the floorplanning problem is an essential design step in VLSI layout design and it is how to place rectangular modules as density as possible. In this paper, we propose a novel constraint driven floorplanning technique based on Genetic Algorithm (GA). Many works have done for the floorplanning problem using GA. However, no studies have ever ...

Floorplanning is an essential design step for hierarchical building module design methodology. Floorplanning provides early feedback that evaluates architectural decisions, estimates chip area, estimates delay and congestion caused by wiring. As technology advances, design complexity is increasing and the circuit size is getting larger. To cope with the increasing design complexity, hierarchica...

In current day microprocessors, exponentially increasing power densities, leakage, cooling costs, and reliability concerns have resulted in temperature becoming a first class design constraint like performance and power. Hence, virtually every high performance microprocessor uses a combination of an elaborate thermal package and some form of Dynamic Thermal Management (DTM) scheme that adaptive...

Floorplanning plays an important role in the physical design of very large scale integration (VLSI) circuits. Traditional floorplanners use heuristics to optimize a floorplan based on multiple objectives. Besides traditional floorplanning approaches, some post-floorplanning steps can be applied to consider block flipping, pin assignment and white space distribution to optimize the performance. ...

Floorplanning is the first stage of VLSI physical design. An effective floorplanning engine definitely has a positive impact on chip design speed, quality, and performance. In this article, we present novel mathematical model to characterize nonoverlapping modules, propose flat fixed-outline algorithm based global placement approach using Poisson’s equation. The consists legalization phases. fl...