In this paper we introduce a method for computing the Elmore delay of MOS circuits which relies on a model of the capacitance of MOS devices and a model of the Elmore delay of individual MOS devices. The resistance of a device is not explicitly modelled. The Elmore models are used to compute the Elmore delay and the 50% point delay of CMOS circuits in a static timing veri er. Elmore delays comp...

Elmore delay has been extensively used for interconnect delay estimation because its simplicity of evaluation makes it appropriate for layout design. However, since Elmore delay does not take into account the e ect of inductance, the discrepancy between actual delay and Elmore delay becomes signi cant for longRLC transmission lines, such as for MCM and PCB interconnects. We describe a simple tw...

Closed form solutions for the 50% delay, rise time, overshoot characteristics, and settling time of signals in an RLC tree are presented. These solutions have the same accuracy characteristics as the Elmore delay for RC trees and preserves the simplicity and recursive characteristics of the Elmore delay. The solutions introduced here cover all damping conditions of an RLC circuit including the ...

We present critical-sink routing tree (CSRT) constructions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and “global slack removal” algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimiz...

We present critical-sink routing tree (CSRT) constructions which exploit available critical-path information to yield high-performance routing trees. Our CS-Steiner and "global slack removal" algorithms together modify traditional Steiner tree constructions to optimize signal delay at identified critical sinks. We further propose an iterative Elmore routing tree (ERT) construction which optimiz...

T h e inaccuracy of Elmore delay [3] f o r interconnect delay estimation i s well-documented. However it remains a popular delay measure t o drive performance optimization procedures such as wire-sizing and topology construction. This paper studies the meri ts of incorporating “better-than-Elmore” delay measures into the optimization process. T h e proposed delay metr ics use a table-lookup met...

This paper presents new single-layer, i.e., planarembeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called Planar-DME, consists of two parts. The first algorithm, called Linear-Planar-DME, guarantees an optimal planar zero-skew clock tree (ZST) under the linear delay model. The second algorithm, called Elmore-Planar-DME, use...

The Elmore delay is the metric of choice for performancedriven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. However, for deep submicron technologies, the accuracy of the Elmore delay is insufficient. In this paper, we formulate a delay model using a provably stable two pole waveform response that provides a unique mapping be...

The Elmore delay is the metric of choice for performancedriven design applications due to its simple, explicit form and ease with which sensitivity information can be calculated. However, for deep submicron technologies, the accuracy of the Elmore delay is insufficient. In this paper, we formulate a delay model using a provably stable two pole waveform response that provides a unique mapping be...

This paper presents new single-layer, i.e., planar-embeddable, clock tree constructions with exact zero skew under either the linear or the Elmore delay model. Our method, called Planar-DME, consists of two parts. The rst algorithm, called Linear-Planar-DME, guarantees an optimal planar zero-skew clock tree (ZST) under the linear delay model. The second algorithm, called ElmorePlanar-DME, uses ...