Power gating technique reduces leakage power in the circuit. However, power gating leads to large voltage fluctuation on the power rail during power gating mode to active mode due to the package inductance in the Printed Circuit Board. This voltage fluctuation may cause unwanted transitions in neighboring circuits. In this work, a power gating architecture is developed for minimizing power in a...

A low dropout voltage regulator with small output voltage variations and the ability of wide load current range support is proposed in this paper. In this LDO structure, a recycling folded cascode operational transconductance amplifier is used as an error amplifier, which has high transconductance and therefore high power efficiency. The designed LDO is simulated in 0.18 μm CMOS standard techno...

A high PSRR full on-chip and area efficient low dropout voltage regulator (LDO), exploiting the nested miller compensation technique with active capacitor (NMCAC) to eliminate the external capacitor and improve the high performance. A novel technique is used to boost the important characteristic for wireless applications regulators PSRR. The idea is applied to stabilize the Low dropout regulato...

i ABSTRACT The partially-depleted (PD) silicon Metal Semiconductor Field Effect Transistor (MESFET) is becoming more and more attractive for analog and RF applications due to its high breakdown voltage. Compared to conventional CMOS high voltage transistors, the silicon MESFET can be fabricated in commercial standard Silicon-on-Insulator (SOI) CMOS foundries without any change to the process. T...

Designed a Low-Dropout (LDO) Regulator, analyzed the circuit structure and the sub-circuit design With On-chip Frequency Compensation. Presented a novel internal frequency compensation circuit, fulfilled the use of low equivalent series resistance (ESR) load capacitor, and an accurate over-current protection circuit is realized, thus improves transient response and reduce the cost greatly. Test...

The proposed CMOS Low Dropout (LDO) regulator has been designed and simulated using TSMC 0.25μ CMOS process in cadence analog design environment . This paper illustrates the design criteria and corresponding analysis relevant to LDO. The experimental result shows that, it regulates an output voltage at 3.3V from a 3.5V supply, with a minimum dropout voltage of 200mV at a maximum output current ...

A low-power fast-transient on-chip low-dropout regulator (LDO) using advanced reference buffer is presented in this paper. The advanced reference buffer is proposed to provide the reference voltage of the LDO with more accurate level to improve the regulation performances. Moreover, in order to suppress the undershoot, the advanced reference buffer increases the reference voltage of the LDO abr...

In this paper, Digital Low Dropout Regulator (LDO) is proposed to provide the low noise and tunable power supply voltage to the 0.5-V near-threshold logic circuits. Because the conventional LDO feedback-controlled by the operational amplifier fail to operate at 0.5 V, the digital LDO eliminates all analog circuits and is controlled by digital circuits, which enables the 0.5-V operation. The dev...

The study of power management techniques has increased drastically within the last few years corresponding to the vast increase in the use of portable, handheld battery applications. These power management systems typically contain several LDO voltage regulators that require large external capacitors. The large external capacitors can not be fully integrated in standard CMOS technologies and hi...