We investigated the source-to-drain capacitance (Csd) due to DIBL effect of silicon nanowire (SNW) MOSFETs. Short-channel SNW devices operating at high drain voltages have the positive value of Csd by DIBL effect. On the other hand, junctionless SNW MOSFETs without source/drain (S/D) PN junctions have negative or zero values by small DIBL effect. By considering the additional source-todrain cap...

This paper has studied drain induced barrier lowering(DIBL) for Double Gate MOSFET(DGMOSFET) using analytical potential model. Two dimensional analytical potential model has been presented for symmetrical DGMOSFETs with process parameters. DIBL is very important short channel effects(SCEs) for nano structures since drain voltage has influenced on source potential distribution due to reduction o...

Statistical variability and reliability due to random discrete dopants (RDD), gate line edge roughness (LER), metal gate granularity and N/PBIT associated random charge trapping has limited the progressive scaling of bulk planar MOSFETs beyond the 20-­‐nm technology ...

Triple Material (TM) Double Gate (DG) Metal Oxide Semiconductor Field Effect Transistor (MOSFET) with high-k dielectric material as Gate Stack (GS) is presented in this paper. A lightly doped channel has been taken to enhance the device performance and reduce short channel effects (SCEs) such as drain induced barrier lowering (DIBL), sub threshold slope (SS), hot carrier effects (HCEs), channel...

This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CGD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the re...

In this paper, degradation effects, such as self-heating effect (SHE) and drain-induced barrier lowering (DIBL) in 2D MoS2-based MOSFETs are investigated through simulations. The SHE is simulated based on the thermodynamic transport model. dependence of DIBL lattice temperature middle channel gate length considered for transistors with different oxide back (BOX) materials. effects Al2O3 HfO2 Si...

This paper investigates the origins of sub-threshold slope degradation in vertical MOSFETs (v-MOSFETs) due to dry etching of the polysilicon surround gate. Control v-MOSFETs exhibit a degradation of subthreshold slope as the channel length is reduced from 250 to 100 nm, with 100 nm transistors having a value of 125 mV/dec and a DIBL of 210 mV/V. The effect of the polysilicon gate etch is invest...

In this work, we investigate the performance of 18nm gate length AlInN/GaN Heterostructure Underlap Double Gate MOSFETs, using 2D Sentaurus TCAD simulation. The simulation is done using the hydrodynamic model and interface traps are also considered. Due to large twodimensional electron gas (2DEG) density and high velocity, the maximal drain current density achieved is very high. Extensive devic...

Multi-gate MOSFETs has shown better results in subthreshold performances. The replacement of SiO2 by high-k dielectric can fulfill the requirements of Multi-gate MOSFETS with scaling trend in device dimensions. The advancement in fabrication technology has also boosted the use of different high K dielectric materials as oxide layer at different places in MOSFET structures. One of the most impor...

The low frequency noise in Silicon Nanowire Field Effect Transistors is analyzed by characterizing the gate electrode dependence on various geometrical parameters. It shows that gate electrodes have a strong impact in the flicker noise of Silicon Nanowire Field effect transistors. Optimization of gate electrode was done by comparing different performance metrics such a DIBL, SS, Ion / Ioff and ...