in this paper, a high speed delay-locked loop (dll) architecture ispresented which can be employed in high frequency applications. in order to design the new architecture, a new mixed structure is presented for phase detector (pd) and charge pump (cp) which canbe triggered by double edges of the input signals. in addition, the blind zone is removed due to the elimination of reset signal. theref...

In this paper, a high speed delay-locked loop (DLL) architecture ispresented which can be employed in high frequency applications. In order to design the new architecture, a new mixed structure is presented for phase detector (PD) and charge pump (CP) which canbe triggered by double edges of the input signals. In addition, the blind zone is removed due to the elimination of reset signal. Theref...

iii ACKNOWLEDGEMENTS I would like to express my sincere gratitude and appreciation to everyone who has helped to make this thesis possible. I would like to deliver my special thanks to my wife and my parents for their love, support, and patience. My deep appreciation also goes to Alfred Andrew for their time and valuable suggestions. Finally, I owe gratitude to all of my friends and colleagues ...

Settling time is one of the most important parameter in design of DLLs. In this paper we propose a new high speed with low settling time Delay Locked Loop (DLL) in which a digital signal processor (DSP) is used instead of using phase-frequency detector, charge pump and loop filter in conventional DLL. To have better settling time, PRP conjugate gradient algorithm is used to optimize delay of ea...

This paper presents analyses and experimental results on the jitter transfer of delay-locked loops (DLLs). Through a -domain model, we show that in a widely used DLL configuration, jitter peaking always exists and high-frequency jitter does not get attenuated as previous analyses suggest. This is true even in a firstorder DLL and an overdamped second-order DLL. The amount of jitter peaking is s...

This paper proposes a digital delay locked loop (DLL) with monotonic line (DL). DLL adopts the calibration mode to reduce non-monotonic effects for coarse-tuning (CTDL) and fine-tuning (FTDL). The detects time of unit, timing resolution CTDL, adjust range FTDL. Thus, can limit overlap between CTDL proposed was implemented using 0.18-μm CMOS process, RMS peak-to-peak jitters were 0.21% 1.72%, re...

The influence of code synchronization errors on the performance of direct-sequence spread-spectrum (DS/SS) communication systems is investigated. Insight is gained in the degradation of some basic performance parameters due to the tracking bias of a noncoherent delay lock loop (DLL). The performance parameters investigated are the bit-error probability, throughput and delay. Numerical results s...

High-speed links which employ source synchronous clocking architectures have the ability to track correlated jitter between clock and data channels up to high frequencies. However, system timing margins are degraded by channel skew between clock and data signals and high-frequency loss. This paper describes how these key channel effects impact the jitter performance and influence the clocking a...