A method to eliminate the effect of capacitor mismatch for a switched-capacitor DAC is described. The method consists of two elements. The first element is the use of a compensating switching algorithm, which can eliminate the effect of capacitor mismatch only for some digital input values. The second element is that each digital word is written as the sum of two other words for which the capac...

A simple but accurate pseudo-passive mismatch-shaping D/A converter is described. A digital state machine is used to control the switching sequence of a symmetric two-capacitor network that performs the D/A conversion. The error caused by capacitor mismatch is uncorrelated with the input signal and has only little power in the signal band. The system has been simulated assuming a 0.1% capacitor...

An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in the conversion time, the first-order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain-and offset-compensated opamp is explained. SWIT-CAP simulation...

A novel two-split capacitor (T-SC) array structure for Successive Approximation Register (SAR) analog-to-digital converter (ADC) is proposed. When used as digital –to-analog converter (DAC), this circuit reduced the chip area by 27.7% in comparing with the conventional Split Capacitor (SC) at resolution=14. The area reduction effect can be more significant with the increasing resolution of ADC....

The presented work deals with analysis of non-ideal effect of pipelined analog-to-digital converter (ADC) such as random capacitor mismatch, comparator offset and finite op-amp gain. These factors arise during a conversion in the pipelined ADC when using CMOS technology and switched-capacitors (SC) technique. The pipelined ADC was simulated in MATLAB-Simulink simulation environment. Key-Words: ...

The mismatch results from the manufacturing error of the capacitor that composes internal DAC deteriorated SNR and THD. This paper presents a new back-ground digital calibration method for precise and high-speed mismatch detection of a pipelined ADC. In the conventional method, the mismatch of the capacitor cannot be detected accurately. The proposed method is a combination of high-pass delta-s...

An alternative method for characterizing capacitor matching is presented. The basic idea of this method is to sense the mismatch among the capacitors by amplifying the error voltage using an iterative switched-capacitor scheme. Through simulation, this method has shown attractive property for sensing capacitor mismatches down to 1% and smaller.

The paper deals with a new 12-bit low power switched-capacitor (SC) ADC for portable applications, such PDA, notebook etc. The paper describes design of ADC and its behavioural modelling regarding low power consumption. The Op-Amp sharing technique and capacitor scaling approach are utilized to obtain it. The basic block topology design is outlined too. The cancellation techniques to avoid the ...

This paper proposes a 1.5 V 12-b CMOS ratio-independent algorithmic analog-to-digital converter (ADC) based on a capacitor-mismatch insensitive technique. A novel switched-capacitor multiplying digital-to-analog converter (MDAC) with an accurate gain of two is proposed for an algorithmic ADC. The proposed MDAC architecture requires only one opamp in four phases to generate the next residue outp...

This paper develops an analytical model for a standard topology, fully differential, switched capacitor amplifier; including the base amplifier offset voltage and common mode range, and capacitor mismatch effects. The amplifier is designed in a 0.6 μm process and the analytical model accuracy is compared with the simulation results.