increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...

increasing the number of cores integrated on a chip and the problems of system on chips caused to emerge networks on chips. nocs have features such as scalability and high performance. nocs architecture provides communication infrastructure and in this way, the blocks were produced that their communication with each other made noc. due to increasing number of cores, the placement of the cores i...

In this paper, we propose a multi-mode router, which supports three modes: bypass, bufferless and normal. By using the power gating technology, it can dynamically switch modes under different network loads, and effectively reduce the power consumption. Besides, in the bufferless mode, we propose an input priority judgment method and an output port allocation method to reduce the packet deflecti...

Kemajuan teknologi informasi yang semakin kencang harus diimbangi dengan kemampuan untuk melakukan pengamanan terhadap informasi. Berbagai masalah penyerangan jaringan bertujuan merugikan pengguna perlu kita pahami bagaimana konsep tersebut. Serangan MITM (Man In The Middle) membelokan traffic paket data melewati perangkat penyerang. Perangkat penyerang mengaku sebagai router ketika berkomunika...

Network-on-Chip (NoC) designs have emerged as a replacement for traditional shared-bus designs for on-chip communications. Typically, these systems require fully balanced clock distribution trees to enable synchronous communication between all nodes on-chip, resulting in higher power consumption. One approach to reduce power consumption is to replace the balanced clock tree with a globally-asyn...

SMART NoC, which transmits unconflicted flits to distant processing elements (PEs) in one cycle through the express bypass, is a high-performance NoC design proposed recently. However, if contention occurs, with low priority would not only be buffered but also could fully utilize bypass. Although there exist several routing algorithms that decrease contentions by rounding busy routers and links...

A conventional Network-on-Chip (NoC) router uses input buffers to store in-flight packets. These buffers improve performance, but consume significant power. It is possible to bypass these buffers when they are empty, reducing dynamic power, but static buffer power remains, and when buffers are utilized, dynamic buffer power remains as well. To improve energy efficiency, bufferless deflection ro...

To meet the performance and scalability demands of the fast-paced technological growth towards exascale and big data processing with the performance bottleneck of conventional metal-based interconnects (wireline), alternative interconnect fabrics, such as inhomogeneous three-dimensional integrated network-on-chip (3D NoC) and hybrid wired-wireless network-on-chip (WiNoC), have emanated as a cos...

A new internetworking architecture based on the Cell Switch Router (CSR) was described. Possible use and protocol overview of the CSR, and migration scenario from conventional ATM internetwork-ing architecture based on the ATM Forum's LAN Emulation or IETF's RFC1577 to CSR-based inter-networking which would cooperate with the MPOA-based architecture was investigated. It provides users with high...