In this paper, footless domino logic buffer circuit is proposed. It minimizes redundant switching at the dynamic and the output nodes. This circuit passes propagation of precharge pulse to the dynamic node and avoids precharge pulse to the output node which saves power consumption. Simulation is done using 0. 18μm CMOS technology. We have calculated the power consumption, delay and power delay ...

A new CMOS buffer without short-circuit power consumption is proposed. In this work, the gate-driving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The TSPICE simulations are used to verify the operation of the buffer. It is observed that the power...

Abstract— This paper presents a new tracking circuit design without standby leakage current issue for 2.5V/3.3V tolerant I/O buffer, which is suitable for the I/O cells in the mixedvoltage applications with different driving capabilities. One set of mixed-voltage I/O cell with the new proposed 2.5V/3.3V tolerant I/O buffer circuit has been designed and drawn in a 0.13-μm salicided CMOS process....

A digital CMOS buffer circuit with a voltage transfer characteristic (VTC) with low threshold voltage detection, hysteresis, and high noise immunity is presented. The circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty, offering at the same time high noise immunity to glitches induced either through capacitive coupling or from the power...

A rail-to-rail class-AB CMOS buffer is proposed in this paper to drive large capacitive loads. A new technique is used to reduce the leakage power of class-AB CMOS buffer circuits without affecting dynamic power dissipation .The name of applied technique is LECTOR, which gives the high speed buffer with the reduced low power dissipation (1.05%) and reduced area (2.8%). The proposed buffer is si...

Performance studies, linking ATM switch capabilities to physical limitations imposed by integrated circuit technology, have been scarce. This paper explores trends in circuit capabilities, and makes projections toward the 0.25m technologies that will be available to all switch designers in the year 2000. The limits imposed by circuit technology are applied to shared buffer ATM switches. We dete...

A new CMOS buffer without short-circuit power consumption is proposed. The gatedriving signal of the output pull-up (pull-down) transistor is fed back to the output pull-down (pull-up) transistor to get tri-state output momentarily, eliminating the short-circuit power consumption. The HSPICE simulation results verified the operation of the proposed buffer and showed the power-delay product is a...