نتایج جستجو برای: adder
تعداد نتایج: 3231 فیلتر نتایج به سال:
شب¬پره¬ی پشت الماسی،plutella xylostella (l.) (lepidoptera: plutellidae) ، آفت جدی کلزا brassica napus l در اردبیل می¬باشد. مقاومت 19 رقم کلزا نسبت به شب¬پره¬ی پشت الماسی به¬ترتیب در سه آزمایش متوالی شامل (1) غربال¬سازی مزرعه¬ای، (2) ترجیح تخم¬گذاری و (3) مطالعه¬ی چرخه¬ی زندگی ارزیابی شد. نتایج غربال-سازی مزرعه¬ای نشان داد که تعداد لاروها و شفیره¬های شب¬پره¬ی پشت الماسی به¬ترتیب روی رقم¬های elit...
we proposed a new adder design, called VariableLatency Adder (VL-adder). This technique allows the adder to work at a lower supply voltage than that required by a conventional adder, while maintaining the same throughput. The VL-adder design can be further modified to overcome the effects of Negative Bias Temperature Instability (NBTI) on circuit delay. By applying VL-adder concept to 64-bit ca...
In this paper, Carry Tree Adders are Proposed. Parallel prefix adders have the best performance in VLSI Design. Parallel prefix adders gives the best performance compared to the Ripple Carry Adder (RCA) and Carry Skip Adder (CSA). Here Delay measurements are done for Kogge-Stone Adder, Sparse Kogge-Stone Adder and Spanning Tree Adder. Speed of Kogge-Stone adder and Sparse Kogge-Stone adder have...
This paper proposes a full adder with minimum power consumption and lowloss with a central frequency of 1550nm using plasmonic Metal-Insulator-Metal (MIM)waveguide structure and rectangular cavity resonator. This full adder operates based onXOR and AND logic gates. In this full adder, the resonant wave composition of the firstand second modes has been used and we have ob...
A fast low-power 1-bit full adder circuit suitable for nano-scale CMOS implementation is presented. Out of the three modules in a common full-adder circuit, we have replaced one with a new design, and optimized another one, all with the goal to reduce the static power consumption. The design has been simulated and evaluated using the 65 nm PTM models.
The proposed multiplexer-based novel 1-bit full adder cell is schematized by using DSCH2 and its layout is generated by using microwind VLSI CAD tool. The adder cell layout interconnect analysis is performed by using BSIM4 layout analyzer. The adder circuit is compared with other six existing adder circuits for parametric analysis. The proposed adder cell gives better performance than the other...
In this paper, we propse 16-bit sparse tree RSFQ adder (Rapid single flux quantam), kogge-stone adder, carry lookahead adder. In general N-bit adders like Ripple carry adder s(slow adders compare to other adders), and carry lookahead adders(area consuming adders) are used in earlier days. But now the most of industries are using parallel prefix adders because of their advantages compare to kogg...
A four port network adder-subtractor module, for surface plasmon polariton (SPP) waves based on a ring resonator filter is proposed. The functionality of module is achieved by the phase difference manipulation of guided SPPs through different arms connected to the ring resonator. The module is designed using the concepts of a basic two-port device proposed in this paper. It is shown that two po...
In this paper, a new low-voltage low-power CMOS 1-bit full adder circuit is proposed. The proposed full adder can provide a full voltage swing at a low supply voltage and offers superior performance in both power and speed than the conventional full adder, the transmission full adder, and the recent low-voltage full adder. Based on the simulation results performed by HSPICE, the new low-voltage...
A carry-select adder can be implemented by using single ripple carry adder and an add-one circuit [1] instead of using dual ripple-carry adders. This paper proposes a new add-one circuit using the first zero finding circuit and multiplexers to reduce the area and power with no speed penalty. For bit length n = 64, this new carry-select adder requires 38 percent fewer transistors than the dual r...
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