Memory access l atencies have become a major bottleneck in the performance of modern computer systems. It has been observed that the SPECint2000 benchmark suite suffers particularly high performance penalties from instruction and data cache misses. Current hardware-based and softwarebased prefetch mechanisms cannot always learn access patterns early enough to avoid compulsory data cache misses....

Trace reuse improves the performance of processors by skipping the execution of sequences of redundant instructions. However, many reusable traces do not have all of their inputs ready by the time the reuse test is done. For these cases, we developed a new technique called Reuse through Speculation on Traces (RST), where trace inputs may be predicted. This paper studies the limits of RST for mo...

the aim of the study was to determine the farmer's behavior in adoption of ipm technologies in rice growing fields. a questionnaire was employed as the tool of survey. population of the study consisted of the farmers taking apart in ipm/ffs participant groups in gilan and mazandaran provinces each with 3 years of experience in ipm. from among them, 305 were selected as the research sample....

the measurement of rts amounts measures a relationship between inputs and outputs in a production structure. there are many different ways to calculate rts in primal or dual space. but in more realistic cases, governments usually intervene on dmu’s behavior as regulatory agency, this clearly represent a set of limitations and restrictions on behaviors of dmus, so very few decisions in dmus are ...