328 0740-7475/05/$20.00 © 2005 IEEE Copublished by the IEEE CS and the IEEE CASS IEEE Design & Test of Computers THERE IS RENEWED INTEREST in using hardware redundancy to mask faulty behavior in nanoelectronic components. In this article, we go back to the early ideas of von Neumann and review the key concepts behind Ntuple modular redundancy (NMR), hardware multiplexing, and interwoven redunda...

One of the most significant challenges facing the development of linear optics quantum computing (LOQC) is mode-mismatch, whereby photon distinguishability is introduced within circuits, undermining quantum interference effects. We examine the effects of mode-mismatch on the parity (or fusion) gate, the fundamental building block in several recent LOQC schemes. We derive simple error models for...

We propose a new class of unconventional geometric gates involving nonzero dynamic phases, and elucidate that geometric quantum computation can be implemented by using these gates. Comparing with the conventional geometric gate operation, in which the dynamic phase shift must be removed or avoided, the gates proposed here may be operated more simply. We illustrate in detail that unconventional ...

This paper describes the fault-tolerant computing research currently active at Stanford University’s Center for Reliable Computing. One focus is on tolerating hardware faults by means of software (software-implemented hardware fault tolerance). This work mainly targets faults caused by radiation induced upsets. An experiment evaluating the techniques that we have developed, is currently running...

This paper presents an electrical stimulator with four high-voltage-tolerant output channels for cochlear implant in a 0.18μm low-voltage CMOS process. As the maximum stimulation voltage can be as high as 7 V, this stimulator only needs one single supply voltage of 1.8 V. To implement this stimulator in a low-voltage CMOS process, the dynamic bias technique and stacked MOS configuration are use...

In this paper we investigate the effect of dephasing on proposed quantum gates for the solid-state Kane quantum computing architecture. Using a simple model of the decoherence, we find that the typical error in a CNOT gate is 8.3 × 10. We also compute the fidelities of Z, X, Swap, and Controlled Z operations under a variety of dephasing rates. We show that these numerical results are comparable...

Quantum dot cellular Automata (QCA) is leading technology for alternative of CMOS design. Reversible Logic design is found to be Low power design which becomes emerging technology in Low power Nanotechnology era. In this work we devoted to design a Reversible Logic Gate which is a universal gate (known as URLG) and can be design with alternative of co-planer cross over wire. We introduce a pass...

This article presents a gate driver circuit with all-magnetic isolation for driving silicon carbide (SiC) power devices in three-level T-type bridge-leg. Gate circuitry SiC has to be tolerant of rapid common-mode voltage changes. With respect the resultant potentially problematic current paths, an arrangement transformers is proposed supplying drive signals and their local floating circuits. Th...

We demonstrate the quantum mean estimation algorithm on Euclidean lattice field theories. This shows a quadratic advantage over Monte Carlo methods which persists even in presence of sign problem, and is insensitive to critical slowing down. The used compute $\pi$ with without toy U(1) gauge theory model, Ising model. effect $R_{Z}$-gate synthesis errors future fault-tolerant computer investiga...

The homogeneous structure of field programmable gate arrays (FPGAs) suggests that the defect tolerance can be achieved by shifting the configuration data inside the FPGA. This paper proposes a new approach for tolerating the defects in FPGA’s configurable logic blocks (CLBs). The defects affecting the FPGA’s interconnection resources can also be tolerated with a high probability. This method is...