In FPGAs, the internal connections in a cluster of lookup tables (LUTs) are often fully-connected like a full crossbar. Such a high degree of connectivity makes routing easier, but has significant area overhead. This paper explores the use of sparse crossbars as a switch matrix inside the clusters between the cluster inputs and the LUT inputs. We have reduced the switch densities inside these m...

In this paper we propose a self-addressing framework for mobile ad hoc networks (MANETs) based on the degenerated use of network address translation (NAT) where each node builds its private “address map”. In contrast to previous proposals, MANET nodes do not need to coordinate in order to generate unique (IP) addresses. This solves an important autoconfiguration problem for MANETs and fits well...

We provide a linear-time algorithm for determining the minimum separation required to route a channel when the connections can be realized in one layer. Differing from the usual “river-routing” context, we allow single-sided connections. The algorithm also works directly for problems with multiterminal nets and does not require wires to lie on an underlying grid, though it does use the rectilin...

This paper analyzes the behavior of callers responding to a speech recognition system when prompted either with an open or a directed dialog strategy. The results of two usability studies with different caller populations are presented. Differences between the results from the two studies are analyzed and are shown to arise from the differences in the domains. It is shown that it depends on the...

Scan chain insertion can have large impact on routability, wirelength and timing. We propose a routing-driven and timing-aware methodology for scan insertion with minimum wirelength. We take into account timing slacks at all sinks that are affected by scan insertion, to achieve a scan chain ordering that meets timing and has smallest wirelength. For the case where sink timing is not met, we als...

As a good trade-off between CPU and ASIC, FPGA is becoming more widely used in both industry and academia. The increasing complexity and scale of modern FPGA, however, impose great challenges on the FPGA placement and packing problem. In this paper, we propose RippleFPGA to solve the packing and placement simultaneously through a set of novel techniques, such as (i) smooth stair-step flow, (ii)...

Yaoguang Wei, University of Minnesota Cliff Sze, IBM Austin Research Laboratory Natarajan Viswanathan, IBM Systems and Technology Group Zhuo Li, IBM Austin Research Laboratory Charles J. Alpert, IBM Austin Research Laboratory Lakshmi Reddy, IBM Systems and Technology Group Andrew D. Huber, IBM Systems and Technology Group Gustavo E. Tellez, IBM Systems and Technology Group Douglas Keller, IBM S...

Placement of multiple dies on an MCM or high-performance VLSI substrate is a non-trivial task in which multiple criteria need to be considered simultaneously to obtain a true multi-objective optimization. Unfortunately, the exact physical attributes of a design are not known in the placement step until the entire design process is carried out. When the performance issues are considered, crossta...

We develop a simple linear time algorithm to determine if a collection of two pin nets can be routed, topologically, in a plane (i.e. single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarngg1].