Stationary random-access memory (SRAM) undergoes an expansion stage, to repel advanced process variation and support ultra-low power operation. Memories occupy more than 80% of the surface in today’s microdevices, this trend is expected continue. Metal oxide semiconductor field effect transistor (MOSFET) face a set difficulties, that results higher leakage current (Ileakage) at lower strategy c...

This research aims to fill up the gap in energy-efficient transistor-level wide word-length carry circuit generator by using ripple (RC) and look-ahead (CLA) method-based hybrid 4-bit generation process for carry-select adder (CSLA). Compared existing CLA architectures, proposed RC-CLA showed performance improvement terms of power delay product (PDP). Later, architectures (existing proposed) we...

An innovative 8 transistor (8T) static random access memory (SRAM) architecture with a simple and reliable read operation is presented in this study. LTspice software used to implement the suggested topology 16nm predictive technology model (PTM). Investigations into comparisons conventional 6T, 8T, 9T, 10T SRAM cells have been made regarding write operations' delay power consumption as well pr...

This paper presents the design of high-speed full adder circuits using a new CMOS mixed mode logic family. The objective of this work is to present a new full adder design circuits combined with current mode circuit in one unit to implement a full adder cell. This paper also discusses a highspeed hybrid majority function based 1-bit full adder that uses MOS capacitors (MOSCAP) in its structure ...

This article presents a new approach for improving the power-delay performance of subthreshold source-couple logic (STSCL) circuits. Using a simple two-phase pipelining technique, it is possible to increase the activity rate of STSCL gates with negligible additional cost, and hence reduce the total system energy consumption per operation. In the proposed pipelined topology, each STSCL gate is f...

In this review paper different design techniques of multi bit adder are deliberate using linear parameters logic gates. The comparison is carried by several parameter mainly focus on a number of linear threshold gates, a number of CMOS transistor, power dissipation, power delay product (PDP), average power dissipation time delay and size of the full adder circuit. Adder circuits basically imple...

This paper proposes the carbon nano structures particularly Carbon nanotube (CNT), Graphene Nanoribbon (GNR), with excellent electrical, thermal and mechanical properties making them an emerging alternative for future onchip interconnect applications. Analysis of CNT and GNR as onchip interconnect has been performed with the help of existing equivalent circuit model. Performance metrics such as...

Different adder circuits are elementary blocks in many contemporary integrated circuits, which are not only employed to perform addition operations, but also other arithmetic operations such as subtraction, multiplication and division. Full adder is the basic building block of any adder circuit. Area, speed and power are the three main design metrics for any VLSI circuit. In this work, eight di...

Abstract This paper proposes a design of gate all around CNTFET based ternary content addressable memory (TCAM). TCAM cell is designed and simulated in HSPICE using top gated (TG-CNTFET) & CNTTFET (GAA-CNTFET). Dual chirality technique used to i.e. different for n-type p-type which utilizes threshold voltages hence improve the performance. Comparative analysis has been done various paramete...

The objectives of advancing secure, intermittency-tolerant, and energy-aware logic datapaths are addressed herein by developing a spin-based design methodology and its corresponding synthesis steps. The approach selectively-inserts Non-Volatile (NV) Polymorphic Gates (PGs) to realize datapaths which are suitable for intrinsic operation in Energy-Harvesting-Powered (EHP) devices. Spin Hall Effec...