Random device mismatch have a significant impact on the performance of analog circuits. This report discusses the design of a Delay Lock Loop (DLL) which is insensitive to process variation. The DLL is optimized for reduction in the variation of threshold voltage variations and is intended to be used in a clock and data recovery circuit with an input bit rate of 500 Mbps. The performance specif...

During the history of science of computational, many evolutionary algorithms approaches were proposed having more or less success in solving various optimization problems. The algorithm is applied for numerical simulations based on optimized proportional integral derivative (PID) control of an automatic regulator voltage system for nominal system parameters and step reference voltage input illu...

This paper presents a transconductor suitable for implementation in submicron CMOS technology. The transconductor is nearly insensitive for the second-order effects of the MOS transistors, which become more and more prevalent in today’s submicron processes. The transconductor relies on a differential pair with variable degeneration resistance, while the degeneration resistors are “soft-switched...

In this study, two parameters of surface roughness and volumetric material removal rate are optimized based on computational intelligence method. Wire electrical discharge machine is used for machining of cold-work steel 2601. The relation between Input parameters including electrical current, pulse-off time, open-circuit voltage and gap voltage and output parameters is studied via Experimental...

In recent years, active Radio Frequency Identification (RFID) tags have crossed into ultra low power domain. With obvious advantages over passive tags, a setback for active tag growth is the need for battery replacement and limited operational life. Battery life could be extended by scavenging surrounding Wi-Fi signals using rectenna architecture which consists of a receiving antenna attached t...

We present an analytical frequency-domain phase noise model for fractional-N phase-locked loops (PLL). The model includes the noise of the crystal reference, the reference input buffer, the voltage-controlled oscillator (VCO), the loop filter, charge pump device noise, sigma-delta modulator (SDM) noise including its effect on the in-band phase noise. Thermal device noise of the charge pump and ...

The matrix converter instability can cause a substantial distortion in the input currents and voltages which leads to the malfunction of the converter. This paper deals with the effects of input filter type, grid inductance, voltage fed to the modulation algorithm and the synchronous rotating digital filter time constant on the stability and performance of the matrix converter. The studies are ...

A new ac/ac power converter topology, in which all the switches operate in a resonant fashion to reduce switching losses, is proposed. The topology enables conduction-period control of individual current pulses, whereby pulse-width modulation (PWM) could be achieved to a fair degree of accuracy with the associated controller. The scheme implements current peak (resonant) limiting by a simple di...