---In this paper a thorough investigation of resistive logic RCJL gate has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this gate has been obtained by the computer-simulation. Our concept of turn-on delay has been introduced. The effect of overdrive current on turn-on delay for resistive logic gate has been shown. This will provide a bet...

CMOS NAND gate circuit performance degradation caused by a single pMOSFET wearout induced by constant voltage stress in 2.0 nm gate dielectrics is examined using a switch matrix technique. The NAND gate rise time is found to increase by approximately 64%, which may lead to timing errors in high frequency digital circuits. The degraded pMOSFET reveals that a decrease in drive current by 41% and ...

Airport gate assignment is a critical issue for the operation management of an airport. Airport gate assignment is to assign flights to gates according to their real-time arrival time and departure time, such that each flight is assigned to exactly one gate, and there is no conflict between two consecutive flights assigned to the same gate. We formulate the airport gate assignment as a stochast...

This paper presents an area-time-efficient systolic structure for multiplication over GF(2 m ) based on irreducible all-one polynomial (AOP). A novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay is used. Also the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input ...

---In this paper a thorough investigation of resistive logic gate DCI has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this DCI gate has been obtained by the computer-simulation. Our concept of turn-on delay has been introduced. The effect of overdrive current on turn-on delay for resistive logic gate has been shown. This will provide a ...

This paper presents an area-time-efficient systolic structure for multiplication over GF(2 m ) based on irreducible all-one polynomial (AOP). A novel cut-set retiming to reduce the duration of the critical-path to one XOR gate delay is used. Also the systolic structure can be decomposed into two or more parallel systolic branches, where the pair of parallel systolic branches has the same input ...

Multipath is one of the most dominant sources of errors in Global Navigation Satellite Systems (GNSS). In this paper we present two tracking structures with multiple gate delays and compare their performance with the performance of Narrow Correlator and High Resolution Correlator. The performance criteria are based on the Multipath Error Envelopes (MEEs), the Root Mean Square Errors (RMSEs) and...

Gate sizing has a significant impact on the delay, power dissipation, and area of the final circuit. It consists of choosing for each node of a mapped circuit a gate implementation in the library so that a cost function is optimized under some constraints. For instance, one wants to minimize the power consumption and/or the area of a circuit under some user-defined delay constraints, or to obta...

In the previous work the problem of nding gate delays to eliminate glitches has been solved by lin ear programs LP requiring an exponentially large number of constraints By introducing two additional variables per gate namely the fastest and the slow est arrival times besides the gate delay we reduce the number of the LP constraints to be linear in circuit size For example the gate c circuit re...

Short Abstract Most industrial digital circuits contain three-state elements besides pure logic gates. We like to presents a gate delay fault test generator for sequential circuits with standard scan design that can handle three-state elements like bus drivers, transmission gates and pulled busses. The delay test pattern generator is based on a well-proved stuck-at test pattern generator that w...