In this paper we present an efficient method of determining the optimized layout of on chip spiral inductor. The method initially identifies the feasible region of optimization by developing layout design parameter bound curves for a large range of physical inductance values that satisfies the same area specification. For any desired inductance value the upper and lower bounds of the optimizati...

We propose two practical approaches for on-chip inductance extraction to obtain a highly sparsified and accurate inverse inductance matrix K. Both approaches differ from previous methods in that they use circuit characteristics to obtain a sparse, stable and symmetric K, using the concept of resistance-dominant and inductance-dominant lines. Specifically, they begin by finding inductance-domina...

Voltage sags and voltage interruptions are huge power quality problems for many industries. Voltage sags cause apart from eventual tripping, large torque peaks, which may cause damage to the shaft or equipment connected to the shaft. This paper illustrates how the stator flux in a synchronous machine changes during voltage sags. These changes result in torque peaks. An analytical time dependent...

In this paper, based on simulations of top-level interconnects and CMOS devices of industrial 0.18 technology, the rules to screen out those inductive interconnects requiring more accurate RLC considerations, and the victim wires potentially having significant inductive noises are developed. The presented criteria constitute a tighter self-inductance screening rule than those found in previousl...

Rogowski coils are increasingly used for measurement of AC and transient electric currents. Mostly used Rogowski coils now are with circular or rectangular cores. In order to increase the sensitivity of the measurement of Rogowski coil and perform smooth wire winding, this paper studies the effect of increasing the mutual inductance in order to increase the coil sensitivity by presenting the ca...

A closed form expression for the propagation delay of a CMOS gate driving a distributed RLC line is introduced that is within 7% of SPICE simulations for a wide range of RLC loads. This expression is based on the alpha power law for deep submicrometer technologies. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed RC ...

On-Chip inductance modeling of VLSI interconnects is presented which captures 3D geometry from layout design and process technology information. Analytical formulae are derived for quick and accurate inductance estimation which can be used in circuit simulations and whole chip extraction screening process. Circuit simulations show critical global wire inductive effects as well as power and grou...

In this work we present a novel, inductance-based system to measure and control the motion of bellows-driven continuum joints in soft robots. The sensing system relies on coils of wire wrapped around the minor diameters of each bellows on the joint. As the bellows extend, these coils of wire become more distant, decreasing their mutual inductance. Measuring this change in mutual inductance allo...

In this paper, we propose a compact on-chip interconnect model for full-chip simulation. The model consists of two components, a quasi-three-dimensional (3-D) capacitance model and an effective loop inductance model. In the capacitance model, we propose a novel concept of effective width ( ) for a 3-D wire, which is derived from an analytical two-dimensional (2-D) model combined with a new anal...

In literature, it is widely accepted that the design of Class-E Power Amplifier (PA) with finite dc feed inductance requires a long iterative solution procedure. To avoid such iterative solution methods, analytical design equations should be known. The problem associated with the finite dc feed inductance Class-E PA is usually ascribed to the fact that the circuit element values are transcenden...