With a modulo-N accumulator and a set of reference waveforms, a new architecture of high-performance digital frequency synthesizer is devised. The reference waveforms with the same frequency but different phases are passed through a multiplexer to obtain the maximal frequency with an incrementer. A Gray encoder is designed to eliminate the glitch problem. The performance of the synthesizer is i...

A new dual-band fractional-N frequency synthesizer is designed to support both 2GHz and 5GHz. The frequencies of two bands are synthesized by single PLL. It needs only a few additional circuits for dual band and has advantages in power and chip area. The synthesizer is composed of dual-band VCO, prescaler, 8/9 divider, PFD(phase-frequency detector), Charge Pump and LF(loop filter). 0.18um CMOS ...

A s discussed in the previous article, a frequency synthesizer can be thought of as a black box containing being properly connected, translate an input reference signal to a number of output frequencies. The synthesizer implementation as well as its ultimate performance depends heavily on characteristics of the individual components used in the design. Although there is no set definition for th...

Behavioural modeling and simulation of a PLL based integer n frequency synthesizer has been illustrated in this paper. The synthesizer generates a signal of 5.15-5.25 GHz in the UNII (Unlicensed National Information Infrastructure) lower band which is used by IEEE 802.11(a). All the PLL building blocks are modeled and simulated using Simulink. The PLL performance has been evaluated using MATLAB...

With the advances in wireless communication technology over last two decades, the use of fractional-N frequency synthesizers has increased widely in modern wireless communication applications due to their high frequency resolution and fast settling time. The performance of a fractional-N frequency synthesizer is degraded due to the presence of unwanted spurious tones (spurs) in the output spect...

T his series of articles continues with an analysis of PLL synthesizer design trade-offs. The simple single-loop PLL synthesizer approach exhibits various limitations and trade-offs. Thus, achieving a good performance combination (e.g., small step size and low phase noise) usually requires more sophisticated solutions. The common design trade-offs as well as various methods to improve synthesiz...