This paper describes a new schematlc-driven floorplanning algorithm. This algorithm improves on initial constructive placement iteratively not only by selecting the best orientation for the module cells , but also optlmising the floorplan topology through local transformations applied to the polar graph representation of the floorplan. The transformations are easy to implement, efficient to per...

We investigate the problem of decoupling capacitance allocation for power supply noise suppression at floorplan level. First, we assume that a floorplan is given, and consider the decoupling capacitance placement as a post-floorplan step. Second, we consider the decoupling capacitance placement as an integral part of a floorplanning methodology (noise aware floorplanning). In both cases, the ob...

In this paper, we present an optimized design flow to map Register-Transfer-Level (RTL) netlists onto multiple-FPGA architectures. Our FPGA-dedicated method fully exploits design structure by letting the basic design steps technology mapping, hierarchical partitioning, floorplanning and signal flow driven placement, interact. This efficiently reduces runtime and yields design implementations of...

In this chapter, we describe the robust and scalable academic placement tool Capo. Capo uses the min-cut placement paradigm and performs (i) scalable multi-way partitioning , (ii) routable standard-cell placement, (iii) integrated mixed-size placement, (iv) wirelength-driven fixed-outline floorplanning as well as (v) incremental placement.

Floor planning is the primary step of the physical design in the Very Large Scale Integration (VLSI) design flow. It is used to estimate the chip area and wire length prior to the real placement of digital blocks and their interconnections. In the modern physical design of VLSI chips, it is essential to design the chip, which works with multi-supply voltages (MSV). To achieve power optimization...

Simulated annealing algorithms for VLSI layout tasks produce solutions of high quality but are computationally expensive. This thesis examines some parallel approaches to accelerate simulated annealing using message-passing multiprocessors with a hypercube architecture. Floorplanning is chosen as a typical application of annealing in physical design. Different partitioning strategies which map ...

This study examines how different initial design decisions affect the area, timing, and power of technology-mapped designs. ASIC flow, tools used during factors to consider maximize performance ratio are discussed. The ALU (Arithmetic Logic Unit) is a fundamental part all processors. In this study, two ALUs were implemented using types adder circuits: Ripple Carry Adder (RCA) Sklansky adder. Ca...