The novel characteristics of a new type of MOSFET, the hetero-material gate field-effect transistor (HMGFET), are explored theoretically and compared with those of the compatible MOSFET. Two conceptual processes for realizing the HMG structure are proposed for integration into the existing silicon technology. The two-dimensional (2-D) numerical simulations reveal that the HMGFET demonstrates ex...

In this paper we report a study on the small signal characterization and simulation of Single Halo (SH) thin film Silicon-on-Insulators (SOI) nMOSFETs for analog and mixed signal applications. The single halo structure has a high pocket impurity concentration near the source end of the channel and low impurity concentration in the rest of the channel. Besides excellent DC output characteristics...

The 25 nm physical gate length transistor for microprocessor units is scheduled for production on the International Technology Roadmap for Semiconductors (ITRS) roadmap for 2007 [1]. Presently, this pushes device engineers to consider developing such transistors because there is a lag of several years between device design and process integration. This paper reports on the methods and design of...

High performance deep-submicron inversion-mode InGaAs MOSFET with ALD Al2O3 as gate dielectric has been demonstrated. Transistors with gate lengths down to 150 nm have been fabricated and characterized. Record high extrinsic transconductance of 1.1 mS/μm has been achieved at Vds = 2.0 V with 5 nm Al2O3 as gate dielectric. Gm can be further improved to 1.3 mS/μm by reducing the gate oxide thickn...

The novel features of an asymmetric double gate single halo (DG-SH) doped SOI MOSFET are explored theoretically and compared with a conventional asymmetric DG SOI MOSFET. The two-dimensional numerical simulation studies demonstrate that the application of single halo to the double gate structure results in threshold voltage roll-up, reduced DIBL, high drain output resistance, kink free output c...

In this paper, novel hybrid MOSFET(HMOS) structure has been proposed to reduce the gate leakage current drastically. This novel hybrid MOSFET (HMOS) uses source/drain-to-gate non-overlap region in combination with high-K layer/interfacial oxide as gate stack. The extended S/D in the non-overlap region is induced by fringing gate electric field through the high-k dielectric spacer. The gate leak...

In this paper, we propose a novel design analysis for a Junctionless Double Gate Vertical MOSFET (JLVMOS) with metal gate electrode and HfO2, for which the simulations have been performed using TCAD (ATLAS), The simulated results exhibits significant improvements in comparison to conventional JLVMOS device with a polysilicon gate electrode and ITRS values for different node technology . In plac...

Amount of power consumption is one of the important measures of performance of an integrated circuit. CMOS is the latest technology which is in use till date. This paper gives an overview of the power dissipation occurring in CMOS circuit. The paper then describes the advantages and limitations of power optimization techniques of CMOS. As we go deeper into the nanometer scale, MOS transistors f...

In this paper we present a compact model of DoubleGate MOSFET architecture including ballistic and quasiballistic transport down to 20 nm channel length. In addition, this original model takes into account short channel effects (SCE/DIBL) by a simple analytical approach. The quasi-ballistic transport description is based on Lundstrom’s backscattering coefficient given by the socalled flux metho...