The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessar...

A fully integrated CMOS wideband distributed variable delay line for time array beam-formers is presented. The delay line works over a full differential mode, and the delay cell function is based on differential amplifiers with active inductive peaking loads. A delay resolution of 15 ps is obtained with a maximum delay capability of 150 ps. The designed active delay line provides 3 scanning ang...

We report experimental demonstration of an all-optical continuously tunable delay line based on parametric mixing with a total delay range of 7.34 mus. The bit-error rate performance of the delay line was characterized for a 10-Gb/s NRZ data channel. This result is enabled by cascading a discrete delay line that consists of 16 wavelength-dependent delays and a continuously tunable delay stage. ...

This paper proposes a fast-locking digital delay-locked loop (DLL) with multiphase outputs using mixed-mode-controlled delay line (MCDL). The proposed DLL uses a dual-loop technique to control various MOS capacitors and an MOS resistor in the MCDL to improve locking time and reduce static phase error. The chip was fabricated using a 0.35 μm standard CMOS process with a 3.3 V supply voltage. The...

The objective of the thesis is to address the problem of clock skew between two different clock domains in modern day microprocessors due to the process, voltage and temperature (PVT) variations. In order to mitigate the misalignment of the clocks in the different clock domains, a delay line is added in all but the reference clock domain. These delay lines add or subtract the delay (as necessar...

In this paper, the entire process of transmission and reception in a DS-CDMA system, including the spreading , is described as a tapped delay line model with multiple inputs and a single output. This model is then used to design a fractionally spaced decision feedback equalizer with a single input and multiple outputs. In the proposed approach , long codes can be used and channel estimation can...

Current synthetic chemical systems lack the ability to selfmodify and learn to solve desired tasks. In this paper we introduce a new parallel model of a chemical delay line, which stores past concentrations over time with minimal latency. To enable temporal processing, we integrate the delay line with our previously proposed analog chemical perceptron. We show that we can successfully train our...

The delay lines for the Magdalena Ridge Observatory Interferometer in New Mexico are required to provide up to 380m optical path delay with an OPD jitter of better than 15nm, in vacuum, using a single adjustable stroke. In order to meet these demanding requirements in a cost-effective manner a unique combination of techniques has been used in the design and construction of the delay line trolle...

For several specific queueing models with a vacation policy, the stationary system occupancy at the beginning of a random slot is distributed as the sum of two independent random variables. One of these variables is the stationary number of customers in an equivalent queueing system with no vacations. For models in continuous time with Poissonian arrivals, this result is well-known, and referre...

This paper focuses on low cost production testing of the far-out phase noise of PLL ICs using the delay line discriminator method. It describes two different delay line discriminator (DLD) implementations for phase noise measurements at large frequency offsets from the carrier. The calibration method using an FM calibration signal is described in detail, both mathematically and graphically. The...