In any digital circuit surface area and power both are very important parameters. In this paper 4bit full adder using transmission gate is designed. To design 4bit full adder two methods are used. First is semi custom design method and second is full custom design method. In first semi custom design method a layout of 4-bit full adder is designed with available width and length of the transisto...

This paper proposes two reversible logic gates, HNFG and HNG. The first gate HNFG can be used as two Feynman Gates. It is suitable for a single copy of two bits with no garbage outputs. It can be used as “Copying Circuit” to increase fan-out because fan-out is not allowed in reversible circuits. The second gate HNG can implement all Boolean functions. It also can be used to design optimized add...

This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A low power and high performance 9T full adder cell using a design style called “XOR (3T)” is discussed. The designed circuit commands a high degree of regularity and symmetric higher density than the conventional CMOS...

The increasing demand for low power VLSI can be fulfilled to a great extent by making proper changes in the circuit level and architectural level design. Addition is a fundamental operation, as it is used to implement more complex functions such as subtraction, multiplication, division etc. The Manchester Carry Chain adder design is preferred to other adders, regardless the number of bits becau...

Arithmetic and Logic Unit (ALU), core unit of a processor, when used for scientific computations, will spend more time in multiplications. For higher order multiplications, a huge number of adders are to be used to perform the partial product addition. Reducing delay in the multiplier reduces the overall computation time. Wallace multipliers perform in parallel, resulting in high speed. It uses...

Keywords: Self-checking adder Carry-select adder Fault localization Self-repairing adder Multiple faults a b s t r a c t In this paper we propose an area-efficient self-repairing adder that can repair multiple faults and identify the particular faulty full adder. Fault detection and recovery has been carried out using self-checking full adders that can diagnose the fault based on internal funct...

In design of complex arithmetic logic circuits, ground bounce noise, standby leakage current and leakage power are important and challenging issues in nanometer down scaling. In this paper, a low power, low complex and reduced ground bounce noise full adder design based on pass transistor logic (PTL) is proposed. Basically adder is vital part of complex arithmetic logic circuit in arithmetic op...

Quantum-dot cellular automata (QCA) are an emerging technology and a possible alternative for faster speed, smaller size, and low power consumption than semiconductor transistor based technologies. Previously, adder designs based on conventional designs were examined for implementation with QCA technology. This paper utilizes the QCA characteristics to design a fault-tolerant adder that is more...

This paper presents pre-layout simulations of a proposed 8T full adder design using a proposed 3T XNOR gate cell. The proposed design remarkably reduces power consumption hence power-delay product (PDP) over various input voltages and frequencies. It also improves temperature sustainability as compared to the existing 8T full adder. This proves to be a viable option for low power and energy eff...

In order to reduce the silicon area of the chip and optimize the power of arithmetic circuits, this paper proposes a low power carry look-ahead BCD (Binary Coded Decimal) adder which uses a four bit MOCLA (Multiplexer and Or gate based Carry Look Ahead Adder) that forms the basic building block. This proposed MOCLA style uses a 2 input MUX, OR gate and GDI (Gate Diffusion Input) based full adde...