Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical m...

Direct wafer bonding is a method for fabricating advanced substrates for microelectromechanical systems (MEMS) and integrated circuits (IC). The most typical example of such an advanced substrate is the silicon-on-insulator (SOI) wafer. SOI wafers offer many advantages over conventional silicon wafers. In IC technology, the switching speed of circuits fabricated on SOI is increased by 20-50% co...

In this paper, we examine the cycle time and on-time delivery performance of a semiconductor wafer fabrication facility (wafer fab) under critical ratio (CR) dispatch regime. It turns out that determining appropriate due dates for this rule is a critical task. We provide a detailed analysis of the wafer fab behavior for a large range of due date values. From the results of the experiments we de...

Semiconductor wafer fabrication is perhaps one of the most complex manufacturing processes found today. In this paper, we construct a simulation model of part of a wafer fab using ProModel software and analyze the effect of different input variables on selected parameters, such as cycle time, WIP level and equipment utilization rates. These input variables include arrival distribution, batch si...

Three-dimensional IC (3D IC) exhibits various advantages over traditional two-dimensional IC (2D IC), including heterogeneous integration, reduced delay and power dissipation, smaller chip area, etc. Wafer-on-wafer stacking is most attractive for 3D IC fabrication, but it suffers from low compound yield. To improve the compound yield, two efforts have been done in this work. First, a hybrid waf...

Cluster tools, each of which consists of several singlewafer processing chambers and a wafer handling robot, have been increasingly used for diverse wafer fabrication processes. Processes such as some low pressure chemical vapor deposition processes require strict timing control. Unless a wafer processed at a chamber for such a process leaves the chamber within a specified time limit, the wafer...

Dopant impurities were implanted at high dose and low energy (10 cm, 0.5–2.2 keV) into double-side polished 200 mm diameter silicon wafers and electrically activated to form p–n junctions by 10 s anneals at temperatures of 1,025, 1,050, and 1,075 C by optical heating with tungsten incandescent lamps. Activation was studied for P, As, B, and BF2 species implanted on one wafer side and for P and ...

Above wafer topography of the substrate, such as wafer clamps, is known to impact adjacent feature profiles during plasma etching of microelectronic devices. The consequences of subwafer topography, such as electrostatic chucks and cooling channels, on feature profiles is less well characterized. To investigate these issues we have developed and integrated a plasma equipment model and a Monte C...

This work presents two different approaches for the implementation of pseudomorphic high electron mobility transistors (pHEMTs) and planar Gunn diodes on the same gallium arsenide substrate. In the first approach, a combined wafer is used where a buffer layer separates the active layers of the two devices. A second approach was also examined using a single wafer where the AlGaAs/InGaAs/GaAs het...

In this paper we consider the Wafer-to-Wafer Integration problem. A wafer is a p-dimensional binary vector. The input of this problem is described by m disjoints sets (called "lots"), where each set contains n wafers. The output of the problem is a set of n disjoint stacks, where a stack is a set ofm wafers (one wafer from each lot). To each stack we associate a p-dimensional binary vector corr...