We present a new framework in which considerations of both register allocation and instruction scheduling can be applied uniformly and simultaneously. In this framework an optimal coloring of a graph, called the parallelizable interference graph, provides an optimal register allocation and preserves the property that no false dependences are introduced, thus all the options for parallelism are ...

A 61-year-old man presented to the emergency department with second degree burns along his right arm and hand. He reported that his knees suddenly gave out while holding a pot of soup resulting in the scalding liquid spilling over his arm. His medical history is significant for alcohol abuse, chronic obstructive pulmonary disease, atrial fibrillation, congestive heart failure with preserved eje...

Inspired by the work on Boolean games, we present turnbased games where each of the players controls a set of atomic variables and each player wants to achieve some individual goal in such a way that the other players remain unaware of the goal until it is actually achieved. We present definitions of winning such games with hidden goals for different non-cooperative settings, and discuss in whi...

The interaction of register allocation and instruction scheduling is a well-studied problem: Certain ways of arranging instructions within basic blocks reduce overlaps of live ranges, leading to the insertion of less costly spill code. However, there is little previous research on the extension of this problem to global code motion, i .e., the motion of instructions between blocks. We present a...

Managing the permissions of any shared space is challenging, even for highly skilled computer users. This task is particularly daunting for untrained PC users, for whom access control errors are routine and can lead to damaging privacy leaks. A 2003 usability study of the Kazaa peer-to-peer file-sharing network found that many users share their entire hard drive with the rest of the Internet, i...

Product releasing is an essential step of an enzymatic reaction, and a mechanistic understanding primarily depends on the active-site conformational changes and molecular interactions that are involved in this step of the enzymatic reaction. Here we report our work on the enzymatic product releasing dynamics and mechanism of an enzyme, horseradish peroxidase (HRP), using combined single-molecul...

The primary goal of the register allocation phase in a compiler is to minimize register spills to memory. Spill decisions by the allocator are often made based on the costs of spilling a virtual register and, therefore, on an assumed placement of spill instructions. However, because most allocators make these decisions incrementally, placement opportunities can change as allocation proceeds, ca...

To use registers effectively, functional programs rely on interprocedural register allocation. Existing interprocedural strategies adopt a naive approach in the presence of recursion, and spill registers whenever necessary. Moreover, such recursion-induced spills cannot be avoided, even by increasing the supply of registers. In this paper, we describe a strategy that reduces memory spills due t...

In-memory caching of intermediate data and eager combining of data in shuffle buffers have been shown to be very effective in minimizing the re-computation and I/O cost in distributed data processing systems like Spark and Flink. However, it has also been widely reported that these techniques would create a large amount of long-living data objects in the heap, which may quickly saturate the gar...