Abstract This article presents Lock-V, a heterogeneous fault tolerance architecture that explores dual-core lockstep (DCLS) technique to mitigate single event upset (SEU) and common-mode failure (CMF) problems. The Lock-V was deployed in two versions, Lock-VA Lock-VM by applying design diversity processor architectures at the instruction set (ISA)-level. features an Arm Cortex-A9 with RISC-V RV...

Single event upsets (SEU) have been observed in implantable cardiac defibrillators. The incidence of SEUs is well modeled by upset rate calculations attributable to the secondary cosmic ray neutron flux. The effect of recent interpretations of the shape of the heavy ion cross-section curve on neutron burst generation rate calculations is discussed. The model correlates well with clinical experi...

The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the second year of the project, design tools that leverage an established FPGA design environment have been created to visualize and analyze an ...

The paper proposes a comparison between hardware and software solutions for resource partitioning in the scenario of a multi-core based mixed criticality application. A reference avionic application has been implemented in two versions: one using a software partitioning solution and one using a hardware partitioning solution. Both versions of the system have been evaluated using fault injection...

SRAM based reprogrammable FPGA with high-flexibility combined with high-performance have become increasingly important for use in space applications. With the advances in technology, the device size decreasing below nm, FPGAs used in space environment are more susceptible to radiation. The radiation effects can cause Single Event Upset (SEU) which are soft-errors and non-destructive. This can a...

The Reconfigurable Hardware in Orbit (RHinO) project is focused on creating a set of design tools that facilitate and automate design techniques for reconfigurable computing in space, using SRAM-based field-programmable-gate-array (FPGA) technology. In the final year of the project, design tools that have been created to visualize and analyze an FPGA circuit for radiation weaknesses and power i...

The contribution of Coulomb processes induced by incident electrons in single event upset (SEU) sensitivity is investigated. case 65-nm silicon on insulator (SOI) memory studied. Several orbits (GPS, Jupiter Icy Moons Explorer's (JUICE's) orbits) are analyzed. relative importance to the total SEU rate electron, proton, and gamma environments compared. obtained during Earth missions. In environm...

A cell-level radiation hardening by design (RHBD) method based on commercial processes of single event transient (SET) and upset (SEU) is proposed in this paper, which new radiation-hardened D-type flip-flops (DFFs) are designed. An application-specific integrated circuit (ASIC) a million gates level developed DFFs, SEU functional interruption (SEFI) heavy-ion tests carried out. The experimenta...

This article investigates heavy-ion irradiation effects on perpendicular magnetic anisotropy spin-transfer torque tunnel junction devices (PMA STT-MTJs). The radiative campaign took place at the Université Catholique de Leuven (UCL) facility. considered consist of STT p-MTJs purely memories and they were fabricated SPINTEC using most advanced CoFeB-MgO MTJ technology. Single-event upset (SEU) t...

This work analyzes an effect of single-bit error in configuration memory of FPGA. Several fault models are proposed and described in detail. Software estimation of vulnerable bits from bitstream is presented, in conjunction with the SEU hardware emulator, which experimentally tests a correctness of the estimation. Results of several combinational benchmark are presented and s1488 benchmark disc...