new technique, at temperatures of 150°C or 450°C t provides planarization after a very deep etching step silicon is presented. Resist spinning and layer palerning as well as realization of bridges or cantilevers across deep holes becomes possible. The sacrificial wafer bonding technique contains a wafer bond step followed by an etch back. Results of (1) polymer bopding followed by dry etching a...

A technology platform demonstrating wafer-level assembly of heterogeneous technologies based upon vertical wafer stacking is described. This platform offers the potential for low-cost assembly of various compound semiconductor circuits with silicon ICs for wide bandwidth optoelectronic and spaceconservative packaging applications. Process development results obtained to date are presented, and ...

A process to fabricate porous silicon Bragg reflectors patterned on a micrometer lateral scale over wafer areas of several square centimeters is described. This process is based on a new type of projection system involving a megavolt accelerator and a quadrupole lens system to project a uniform distribution of MeV ions over a wafer surface, which is coated with a multilevel mask. In conjunction...

We theoretically and experimentally demonstrate an ultrasensitive two-dimensional photonic crystal microcavity biosensor. The device is fabricated on a silicon-on-insulator wafer and operates near its resonance at 1.58 microm. Coating the sensor internal surface with proteins of different sizes produces a different amount of resonance redshift. The present device can detect a molecule monolayer...

Emissivity is a critical parameter in the rapid thermal processing ~RTP! of semiconductors for temperature control and thermal modeling. It is often considered as a material property that depends on the sample temperature and surface finishing. For a silicon wafer placed in a radiation environment such as a RTP chamber, however, the ambient photons emitted from lamps create electron-hole pairs ...

This paper describes the formation of mono-domain highly ordered nanoporous alumina on the scale of a 2 inch diameter silicon wafer by anodization of aluminium evaporated on a patterned SiO(2) mask on a silicon substrate. The position of the ordered pores correlates with holes in the SiO(2) mask, which guide the electric field during anodization and initiates pore nucleation. The technique is s...

This thesis describes heterogeneous integration methods for the fabrication of microelectromechanical systems (MEMS). Most MEMS devices reuse the fabrication techniques that are found in the microelectronics integrated circuit industry. This limits the selection of materials and processes that are feasible for the realization of MEMS devices. Heterogeneous integration methods, on the other hand...

Silicon nanowires fabricated by metal-assisted chemical etching can present low porosity and a rough surface depending on the doping level of the original silicon wafer. In this case, wiring of silicon nanowires may represent a challenging task. We investigated two different approaches to realize the electrical contacts in order to enable electrical measurement on a rough silicon nanowire devic...

Combining micro-photoluminescence spectroscopy and photoluminescence excitation spectroscopy, we are able to observe the evolution of the luminescence spectra from crystalline silicon wafers under various excitation wavelengths. By interpreting the relative change of the luminescence spectra, we can detect and examine the distributions of the dislocations, as well as of the defects and impuriti...

High pressure-rated channels allow microfluidic assays to be performed on a smaller footprint while keeping the throughput, thanks to the higher enabled flow rates, opening up perspectives for cost-effective integration of CMOS chips to microfluidic circuits. Accordingly, this study introduces an easy, low-cost and efficient method for realizing high pressure microfluidics-to-CMOS integration. ...