| The channel segmentation design problem for symmetrical FPGAs is the problem of designing segmented tracks in the interconnection channels to provide good net routability and delay performance at the same time. In this paper, we show how to decompose the problem into the segmentation design problems of the vertical and horizontal channels by a statistical analysis of the net distribution on a...

Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding the optimal number of sleep transistors and their placement as well as optimal P/G network grids, wire widths and layers. This paper presents a fake via based sleep transistor P/G network synthesis method, which addre...

This paper presents an interconnect-driven floorplanning (IDFP) flow and algorithm integrated with multi-layer global wiring planning (GWP). It considers a number of interconnect performance optimizations during floorplanning, including interconnect topology optimization, layer assignment, buffer insertion, wire sizing and spacing. It also includes fast routability estimation and performance-dr...

As the capacities of eld-programmable gate arrays (FPGAs) grow, it becomes desirable to create FPGAs with embedded memory arrays. This paper examines the exibility of the interconnect structure that joins memory and logic. For architectures with only a few memory arrays, we nd that both the routability and the delay of circuits are insensitive to the memory/logic interconnect exibility, which i...

Most of the proposed security protocols for routing optimization in Mobile IPv6, including the one in the standard, depend on the special relationship between the home network and the mobile node. In this paper, we present a new protocol that does not depend on the security relationship between the home network and the mobile. The security of the protocol is analyzed and its performance evaluat...

Design hierarchy plays an important role in timing-driven placement for large circuits. In this paper, we present a new methodology for delay budgeting based timing-driven placement. A novel slack assignment approach is described as well as its application on delay budgeting with design hierarchy information. The proposed timing-driven placement flow is evaluated using an industrial place and r...

As technology moves into the deep-submicron era, the complexities of VLSI circuits grow rapidly. Interconnect optimization has become an important concern. Most routability-driven floorplanners [H.M. Chen, H. Zhou, F.Y. Young, D.F. Wong, H.H. Yang, N. Sherwani, Integrated floorplanning and interconnect planning, in: Proceedings of IEEE International Conference on Computer-Aided Design, 1999, pp...

Placement of multiple dies on an MCM or high-performance VLSI substrate is a non-trivial task in which multiple criteria need to be considered simultaneously to obtain a true multi-objective optimization. Unfortunately, the exact physical attributes of a design are not known in the placement step until the entire design process is carried out. When the performance issues are considered, crossta...

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We develop a simple linear time algorithm to determine if a collection of two-pin nets can be routed, topologically, in a plane (i.e., single layer). Experiments indicate that this algorithm is faster than the linear time algorithm of Marek-Sadowska and Tarng. Topological routability testing of a collection of multipin nets is shown to be equivalent to planarity testing, and a simple linear tim...