This brief presents a new tristate-based delay cell to realize the recently proposed delay-based injection locking in ring oscillators. The circuit is then applied implement cyclic-coupled oscillator (CCRO). Compared an inverter-based CCRO with multi-drive injection, eliminates static short-circuit current drawn from supply when drive circuits are conflicting logic states, thus reducing power c...

This project evaluate the performance of improved power delay profile estimation in Multiple input multiple output orthogonal frequency division multiplexing (MIMO-OFDM) systems under linear minimum mean square error(LMMSE) channel. The distortions caused by null subcarriers and a short range of samples for PDP estimation is also considered. The proposed technique effectively estimates the dist...

The paper proposed a new design for implementing semi-static flip-flop for low power and high performance applications. In this work, comparative analysis of six existing flip-flop designs along with the proposed design is made. The proposed design has better power, delay and PDP than the existing architectures. All simulations are performed on TSpice using BSIM models in 130 nm process node. T...

As technology has scaled down, the implications of leakage current and power analysis for memory design have increased. To minimize the short channel effect Double-gate FinFET can be used in place of conventional MOSFET circuits due to the self-alignment of the two gates. Design for XOR and XNOR circuits is suggested to improve the speed and power. These circuits act as basic building blocks fo...

The residue number system is widely used in applications such as communication systems, cryptography, digital filters, signal processors, fault-tolerant detection, and so on. This paper proposes a multifunction modulo (2n ± 1) multiplier based on the radix-4 Booth encoding scheme that can operate both − + multipliers using same hardware structure with only one control signal. A novel proposed a...

In this paper a new design of full adder cell based on Sense Energy Recovery concept using novel exclusive NOR gates is presented. Low-power consumption and delay are targeted in implementation of our design. The circuit designed is optimized for low power at 0.18-μm and 0.09 μm CMOS process technologies in full custom environment. The new circuit has been compared to the existing work based on...

This paper presents two new general threshold gate (GTG) structures which are based on the monostable-bistable element (MOBILE) as their main part. These new GTGs eliminate an RTD from the structure compared to old structures and lead to less elements count and better performance in terms of power consumption, maximum frequency, and power-delay product (PDP). In the paper also two new single ga...

The carry look-ahead adder (CLA) is well known among the family of high-speed adders. However, a conventional CLA not faster than other adders such as conditional sum (CSA), carry-select (CSLA), and Kogge–Stone (KSA), which fastest parallel-prefix adder. Further, in terms power-delay product (PDP) that characterizes energy digital circuits, efficient compared to CSLA KSA. In this context, paper...

Reversible logic has attracted substantial interest due to its low power consumption which is the main concern of low power VLSI circuit design. In this paper, a novel 4x4 reversible gate called inventive gate has been introduced and using this gate 1-bit, 2-bit, 8-bit, 32-bit and n-bit group-based reversible comparator have been constructed with low value of reversible parameters. The MOS tran...

In digital CMOS design, power consumption has been a major concern for several years advanced IC fabrication technology allows the use of nano-scale devices so inability to get power to circuits, power leakage or to remove the heat they generate. By optimizing the transistor size in each stage power and delay can be minimized. This paper presents the analysis of full adders having efficient par...