This paper proposes a System-on-ProgrammableChip (SoPC) architecture to implement a stereo matching algorithm based on the sum of absolute differences (SAD) in a FPGA chip which can provide 1396×1110 disparity maps at 30 fps speed. The hardware implementation involves a 32bit Nios II microprocessor, memory interfaces and stereo matching algorithm circuit module. The stereo matching algorithm co...

This work presents the implementation of a matching-based motion estimation sensor on a Field Programmable Gate Array (FPGA) and NIOS II microprocessor applying a C to Hardware (C2H) acceleration paradigm. The design, which involves several matching algorithms, is mapped using Very Large Scale Integration (VLSI) technology. These algorithms, as well as the hardware implementation, are presented...

As embedded system designs become increasingly more complex, the use of real-time operating systems (RTOS) becomes essential to meet time-to-market pressures and to contain non-recurring engineering costs. However, an RTOS consumes precious CPU cycles in return for the services it provides. Further, the RTOS is typically treated as a pure software entity and is subject only to minor adaptations...

This work presents an efficient fast parallel architecture of the Vector Median Filter (VMF) using combined hardware/software (HW/SW) implementation. The hardware part of the system is implemented using VHDL language, whereas the software part is developed using C/C++ language. The software part of the embedded system uses the NIOS-II softcore processor and the operating system used is μClinux....

The system on chip paradigm consists of one or more instruction set processors integrated with custom hardware on a single integrated circuit. A uni-processor real-time kernel is presented that integrates hardware coprocessors by viewing them as system resources to be scheduled in conjunction with the processor. The kernel implements the earliest-deadline first scheduling policy. To demonstrate...

The reliability of the software chip is the essential factor in VLSI design since the chip can be implanted in any embedded circuit varies from simple adder to crucial satellite device. Thus breach in VLSI chip operation may results in huge negative impact devastation. A novel architecture of VLSI chip testing design is proposed and unlike from normal BIST structure this structure ensures the s...

This paper presents hardware solutions for accelerating IEEE 802.11i. Several experiments were applied on the low-cost Cyclone II FPGA by using various architectures with different number of threads. The FPGA offloads the process of AES encryption from the master CPU. In addition, it offers the possibility of using several threads to run the AES encryption. Different optimizations have been app...