Integration of amorphous diodes with a fully depleted silicon on isolator (FD SOI) MOSFET circuit is first presented in this paper. In addition we present a very simple circuit fabricated in SOI, which when integrated with an amorphous silicon photodiode significantly improves the detection of current variation through the diode, when it is illuminated. The circuit takes advantage of the better...

In this paper we present the results of the implementation of a nanoscale double-gate (DG) MOSFET compact model, which includes hydrodynamic transport model, in Verilog-A in order to carry out circuit simulation. The model in Verilog-A is used with the SMASH circuit simulator for the analysis of the DC and transient behavior electrical CMOS circuits. Template devices representative for a downsc...

Recently analog circuit designers are interested in structured optimization techniques to automate the process of CMOS circuit design. Geometric programming, which makes use of monomial and posynomial expressions to model MOSFET parameters, represents one such approach. The extent of accuracy in finding a global optimal solution using this approach depends on the formulation of circuit and devi...

Exact analytical expressions for the switching delay of an inverter driving an RC load, taking into account the velocity saturation, are obtained. Modified expressions to include theeffectofsource resistance arethen presented.Owing to the limitation on switching current imposed by the velocity saturation mechanism, the switching delay is substantially increased for identical width-io-length rat...

The effect of MOSFET gate-oxide reliability on MOS switch with bootstrapped technique is investigated with the switched-capacitor circuit in a 130-nm CMOS process. The sample-and-hold amplifier with the openloop configuration is used to verify the impact of MOS switch gate-oxide reliability on the switched-capacitor circuit. After overstress on the MOS switch of sampleand-hold amplifier, the ci...

This paper presents a study of Active inductor based VCOs that helps in increasing the tuning range of the VCO , reduces the chip size and phase noise of the circuit. Study has been done on LC VCOs by replacing the passive inductors with the active one consisting of MOSFET. Design of circuit has been done on Orcade Capture using .18um technology.power consumption of circuit is 1.33mW with tunin...

In this paper, an analytical modeling is presentated to describe the channel noise in GME SGT/CGT MOSFET, based on explicit functions of MOSFETs geometry and biasing conditions for all channel length down to deep submicron and is verified with the experimental data. Results shows the impact of various parameters such as gate bias, drain bias, channel length ,device diameter and gate material wo...

The advent of differential voltage current conveyor(DVCC) has opened up new avenues in analog circuit design. In the present work, a DVCC has been employed to designcurrent-mode first-order continuous-time analog filters. Parameter tunability is achieved by the use of a two-MOSFET electronicresistor which exhibits variation in resistance in accordancewith a control voltage. The proposed circuit...

Cdv/dt induced turn-on of the synchronous MOSFET deteriorates performance in synchronous buck regulators. We will discuss this problem and provide several solutions that can reduce the effects. SYNCHRONOUS BUCK REGULATOR Synchronous buck topology is becoming popular in powering ultra-fast CPU cores. A standard buck circuit is shown in Figure 1(a) and a synchronous buck is shown in Figure 1(b). ...