Dynamic Power by internal capacitance * Short-circuit Current Dissipation . ~ ~ ~ ~ ~ i ~ i ~ ~ i~~ 1 I Delay Abstract---It is known that input reordering of a gate affects the power dissipated by the internal capacitance of the reordered gate, which has been utilized for power reduction so far. We show that the reordering also has a significant effect on the power dissipation of the gate which...

--In this paper a thorough investigation of resistive logic gate, JAWS (Josephson Auto-Weber System) has been made. The current equations of this gate at each stage have been deduced. The dynamic response of this gate has been obtained by the computer-simulation. Our concept of turn-on delay of Josephson junction has been introduced. The effect of overdrive current on turn-on delay for JAWS res...

Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from field-effect transistors (FETs) to low-temperature quantum devices. Here we report the first studies of the size-dependent performance limits of Ge/Si NWFETs in the sub-100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub-100 nm Ge/Si cha...

The use of nanometer CMOS technologies (below 90nm) however brings along significant challenges for circuit design (both analog and digital). By reducing the dimensions of transistors many physical phenomenon like gate leakage, drain induced barrier lowering and many more effects comes into picture. Reducing the feature size in the technology of device with the addition of ever more interconnec...

Please cite this article in press as: Hwang E et a logic applications. Solid State Electron (2011), d In this paper, the scalability of In0.7Ga0.3As QWFET is investigated using two-dimensional numerical drift–diffusion simulation. Numerical drift–diffusion simulations were calibrated using experimental results on short-channel In0.7Ga0.3As QWFETs [7] to include the effects of velocity overshoot...

In this paper, we introduce an innovative and systematic technique to study delay differential equations via polynomials. First, we review an intrinsic relation between delay differential equations and polynomials. From this relation, we obtain long time behaviors of the solutions to delay differential equations via asymptotic analysis of the corresponding polynomials. Moreover, we derive asymp...

Semiconductor nanowires are potential alternatives to conventional planar (MOSFETs). Nanowire FETs (NWFETs) have a unique electronic structure which we can try and exploit. Carriers in nanowires have longer mean free paths and are subjected to reduced scattering thanks to onedimensional quantum confinement effects. Unlike carbon-nanotubes (CNTs), the electronic properties of nanowires are highl...

Introduction: The increase of transistor speed in CMOS technologies has been reached mainly by scaling the gate length of the MOS transistors. For the most advanced technologies, gate lengths down to 40 nm with an ft of 243 GHz [1] have been reported. This allows performances comparable to expensive III-V technologies based on GaAs or InP and in addition the potential for very large scale integ...

We propose and analyze the implementation of a two-qubit quantum gate using circular Rydberg states with maximum orbital angular momentum. The intrinsic quantum gate error is limited by the finite Rydberg lifetime and finite Rydberg blockade shift. Circular states have much longer radiative lifetimes than low orbital angular momentum states and are therefore candidates for high-fidelity gate op...

Delay-Insensitive Gate-Level Pipelining S. C. Smith, R. F. DeMara, J. S. Yuan, M. Hagedorn, and D. Ferguson